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Classes |
| struct | _PCI_SLOT_NUMBER |
| struct | _PCI_COMMON_CONFIG |
| struct | _PCI_CAPABILITIES_HEADER |
| struct | _PCI_PMC |
| struct | _PCI_PMC::_PM_SUPPORT |
| struct | _PCI_PMCSR |
| struct | _PCI_PMCSR_BSE |
| struct | _PCI_PM_CAPABILITY |
| struct | _PCI_AGP_CAPABILITY |
| struct | _PCI_AGP_CAPABILITY::_PCI_AGP_STATUS |
| struct | _PCI_AGP_CAPABILITY::_PCI_AGP_COMMAND |
| struct | _PCI_MSI_CAPABILITY |
| struct | _PCI_MSI_CAPABILITY::_PCI_MSI_MESSAGE_CONTROL |
| struct | _PCI_REGISTRY_INFO |
| struct | _PCI_TYPE1_CFG_BITS |
| struct | _PCI_TYPE2_CSE_BITS |
| struct | _PCI_TYPE2_ADDRESS_BITS |
| struct | _PCI_TYPE0_CFG_CYCLE_BITS |
| struct | _PCI_TYPE1_CFG_CYCLE_BITS |
| struct | _PCIBUSDATA |
| struct | _PCI_BUS_INTERFACE_STANDARD |
| struct | _PCI_DEVICE_PRESENT_INTERFACE |
Defines |
| #define | PCI_TYPE0_ADDRESSES 6 |
| #define | PCI_TYPE1_ADDRESSES 2 |
| #define | PCI_TYPE2_ADDRESSES 5 |
| #define | PCI_COMMON_HDR_LENGTH (FIELD_OFFSET (PCI_COMMON_CONFIG, DeviceSpecific)) |
| #define | PCI_MAX_DEVICES 32 |
| #define | PCI_MAX_FUNCTION 8 |
| #define | PCI_MAX_BRIDGE_NUMBER 0xFF |
| #define | PCI_INVALID_VENDORID 0xFFFF |
| #define | PCI_MULTIFUNCTION 0x80 |
| #define | PCI_DEVICE_TYPE 0x00 |
| #define | PCI_BRIDGE_TYPE 0x01 |
| #define | PCI_CARDBUS_BRIDGE_TYPE 0x02 |
| #define | PCI_CONFIGURATION_TYPE(PciData) (((PPCI_COMMON_CONFIG)(PciData))->HeaderType & ~PCI_MULTIFUNCTION) |
| #define | PCI_MULTIFUNCTION_DEVICE(PciData) ((((PPCI_COMMON_CONFIG)(PciData))->HeaderType & PCI_MULTIFUNCTION) != 0) |
| #define | PCI_ENABLE_IO_SPACE 0x0001 |
| #define | PCI_ENABLE_MEMORY_SPACE 0x0002 |
| #define | PCI_ENABLE_BUS_MASTER 0x0004 |
| #define | PCI_ENABLE_SPECIAL_CYCLES 0x0008 |
| #define | PCI_ENABLE_WRITE_AND_INVALIDATE 0x0010 |
| #define | PCI_ENABLE_VGA_COMPATIBLE_PALETTE 0x0020 |
| #define | PCI_ENABLE_PARITY 0x0040 |
| #define | PCI_ENABLE_WAIT_CYCLE 0x0080 |
| #define | PCI_ENABLE_SERR 0x0100 |
| #define | PCI_ENABLE_FAST_BACK_TO_BACK 0x0200 |
| #define | PCI_STATUS_CAPABILITIES_LIST 0x0010 |
| #define | PCI_STATUS_66MHZ_CAPABLE 0x0020 |
| #define | PCI_STATUS_UDF_SUPPORTED 0x0040 |
| #define | PCI_STATUS_FAST_BACK_TO_BACK 0x0080 |
| #define | PCI_STATUS_DATA_PARITY_DETECTED 0x0100 |
| #define | PCI_STATUS_DEVSEL 0x0600 |
| #define | PCI_STATUS_SIGNALED_TARGET_ABORT 0x0800 |
| #define | PCI_STATUS_RECEIVED_TARGET_ABORT 0x1000 |
| #define | PCI_STATUS_RECEIVED_MASTER_ABORT 0x2000 |
| #define | PCI_STATUS_SIGNALED_SYSTEM_ERROR 0x4000 |
| #define | PCI_STATUS_DETECTED_PARITY_ERROR 0x8000 |
| #define | PCI_WHICHSPACE_CONFIG 0x0 |
| #define | PCI_WHICHSPACE_ROM 0x52696350 |
| #define | PCI_CAPABILITY_ID_POWER_MANAGEMENT 0x01 |
| #define | PCI_CAPABILITY_ID_AGP 0x02 |
| #define | PCI_CAPABILITY_ID_MSI 0x05 |
| #define | PCI_AGP_RATE_1X 0x1 |
| #define | PCI_AGP_RATE_2X 0x2 |
| #define | PCI_AGP_RATE_4X 0x4 |
| #define | PCI_CLASS_PRE_20 0x00 |
| #define | PCI_CLASS_MASS_STORAGE_CTLR 0x01 |
| #define | PCI_CLASS_NETWORK_CTLR 0x02 |
| #define | PCI_CLASS_DISPLAY_CTLR 0x03 |
| #define | PCI_CLASS_MULTIMEDIA_DEV 0x04 |
| #define | PCI_CLASS_MEMORY_CTLR 0x05 |
| #define | PCI_CLASS_BRIDGE_DEV 0x06 |
| #define | PCI_CLASS_SIMPLE_COMMS_CTLR 0x07 |
| #define | PCI_CLASS_BASE_SYSTEM_DEV 0x08 |
| #define | PCI_CLASS_INPUT_DEV 0x09 |
| #define | PCI_CLASS_DOCKING_STATION 0x0a |
| #define | PCI_CLASS_PROCESSOR 0x0b |
| #define | PCI_CLASS_SERIAL_BUS_CTLR 0x0c |
| #define | PCI_CLASS_NOT_DEFINED 0xff |
| #define | PCI_SUBCLASS_PRE_20_NON_VGA 0x00 |
| #define | PCI_SUBCLASS_PRE_20_VGA 0x01 |
| #define | PCI_SUBCLASS_MSC_SCSI_BUS_CTLR 0x00 |
| #define | PCI_SUBCLASS_MSC_IDE_CTLR 0x01 |
| #define | PCI_SUBCLASS_MSC_FLOPPY_CTLR 0x02 |
| #define | PCI_SUBCLASS_MSC_IPI_CTLR 0x03 |
| #define | PCI_SUBCLASS_MSC_RAID_CTLR 0x04 |
| #define | PCI_SUBCLASS_MSC_OTHER 0x80 |
| #define | PCI_SUBCLASS_NET_ETHERNET_CTLR 0x00 |
| #define | PCI_SUBCLASS_NET_TOKEN_RING_CTLR 0x01 |
| #define | PCI_SUBCLASS_NET_FDDI_CTLR 0x02 |
| #define | PCI_SUBCLASS_NET_ATM_CTLR 0x03 |
| #define | PCI_SUBCLASS_NET_OTHER 0x80 |
| #define | PCI_SUBCLASS_VID_VGA_CTLR 0x00 |
| #define | PCI_SUBCLASS_VID_XGA_CTLR 0x01 |
| #define | PCI_SUBCLASS_VID_OTHER 0x80 |
| #define | PCI_SUBCLASS_MM_VIDEO_DEV 0x00 |
| #define | PCI_SUBCLASS_MM_AUDIO_DEV 0x01 |
| #define | PCI_SUBCLASS_MM_OTHER 0x80 |
| #define | PCI_SUBCLASS_MEM_RAM 0x00 |
| #define | PCI_SUBCLASS_MEM_FLASH 0x01 |
| #define | PCI_SUBCLASS_MEM_OTHER 0x80 |
| #define | PCI_SUBCLASS_BR_HOST 0x00 |
| #define | PCI_SUBCLASS_BR_ISA 0x01 |
| #define | PCI_SUBCLASS_BR_EISA 0x02 |
| #define | PCI_SUBCLASS_BR_MCA 0x03 |
| #define | PCI_SUBCLASS_BR_PCI_TO_PCI 0x04 |
| #define | PCI_SUBCLASS_BR_PCMCIA 0x05 |
| #define | PCI_SUBCLASS_BR_NUBUS 0x06 |
| #define | PCI_SUBCLASS_BR_CARDBUS 0x07 |
| #define | PCI_SUBCLASS_BR_OTHER 0x80 |
| #define | PCI_SUBCLASS_COM_SERIAL 0x00 |
| #define | PCI_SUBCLASS_COM_PARALLEL 0x01 |
| #define | PCI_SUBCLASS_COM_OTHER 0x80 |
| #define | PCI_SUBCLASS_SYS_INTERRUPT_CTLR 0x00 |
| #define | PCI_SUBCLASS_SYS_DMA_CTLR 0x01 |
| #define | PCI_SUBCLASS_SYS_SYSTEM_TIMER 0x02 |
| #define | PCI_SUBCLASS_SYS_REAL_TIME_CLOCK 0x03 |
| #define | PCI_SUBCLASS_SYS_OTHER 0x80 |
| #define | PCI_SUBCLASS_INP_KEYBOARD 0x00 |
| #define | PCI_SUBCLASS_INP_DIGITIZER 0x01 |
| #define | PCI_SUBCLASS_INP_MOUSE 0x02 |
| #define | PCI_SUBCLASS_INP_OTHER 0x80 |
| #define | PCI_SUBCLASS_DOC_GENERIC 0x00 |
| #define | PCI_SUBCLASS_DOC_OTHER 0x80 |
| #define | PCI_SUBCLASS_PROC_386 0x00 |
| #define | PCI_SUBCLASS_PROC_486 0x01 |
| #define | PCI_SUBCLASS_PROC_PENTIUM 0x02 |
| #define | PCI_SUBCLASS_PROC_ALPHA 0x10 |
| #define | PCI_SUBCLASS_PROC_POWERPC 0x20 |
| #define | PCI_SUBCLASS_PROC_COPROCESSOR 0x40 |
| #define | PCI_SUBCLASS_SB_IEEE1394 0x00 |
| #define | PCI_SUBCLASS_SB_ACCESS 0x01 |
| #define | PCI_SUBCLASS_SB_SSA 0x02 |
| #define | PCI_SUBCLASS_SB_USB 0x03 |
| #define | PCI_SUBCLASS_SB_FIBRE_CHANNEL 0x04 |
| #define | PCI_ADDRESS_IO_SPACE 0x00000001 |
| #define | PCI_ADDRESS_MEMORY_TYPE_MASK 0x00000006 |
| #define | PCI_ADDRESS_MEMORY_PREFETCHABLE 0x00000008 |
| #define | PCI_ADDRESS_IO_ADDRESS_MASK 0xfffffffc |
| #define | PCI_ADDRESS_MEMORY_ADDRESS_MASK 0xfffffff0 |
| #define | PCI_ADDRESS_ROM_ADDRESS_MASK 0xfffff800 |
| #define | PCI_TYPE_32BIT 0 |
| #define | PCI_TYPE_20BIT 2 |
| #define | PCI_TYPE_64BIT 4 |
| #define | PCI_ROMADDRESS_ENABLED 0x00000001 |
| #define | PciBridgeIO2Base(a, b) ( ((a >> 4) << 12) + (((a & 0xf) == 1) ? (b << 16) : 0) ) |
| #define | PciBridgeIO2Limit(a, b) (PciBridgeIO2Base(a,b) | 0xfff) |
| #define | PciBridgeMemory2Base(a) (ULONG) ((a & 0xfff0) << 16) |
| #define | PciBridgeMemory2Limit(a) (PciBridgeMemory2Base(a) | 0xfffff) |
| #define | PCI_ENABLE_BRIDGE_PARITY_ERROR 0x0001 |
| #define | PCI_ENABLE_BRIDGE_SERR 0x0002 |
| #define | PCI_ENABLE_BRIDGE_ISA 0x0004 |
| #define | PCI_ENABLE_BRIDGE_VGA 0x0008 |
| #define | PCI_ENABLE_BRIDGE_MASTER_ABORT_SERR 0x0020 |
| #define | PCI_ASSERT_BRIDGE_RESET 0x0040 |
| #define | PCI_ENABLE_BRIDGE_FAST_BACK_TO_BACK 0x0080 |
| #define | PCI_ENABLE_CARDBUS_IRQ_ROUTING 0x0080 |
| #define | PCI_ENABLE_CARDBUS_MEM0_PREFETCH 0x0100 |
| #define | PCI_ENABLE_CARDBUS_MEM1_PREFETCH 0x0200 |
| #define | PCI_ENABLE_CARDBUS_WRITE_POSTING 0x0400 |
| #define | PCI_TYPE1_ADDR_PORT ((PULONG) 0xCF8) |
| #define | PCI_TYPE1_DATA_PORT 0xCFC |
| #define | PCI_TYPE2_CSE_PORT ((PUCHAR) 0xCF8) |
| #define | PCI_TYPE2_FORWARD_PORT ((PUCHAR) 0xCFA) |
| #define | PCI_TYPE2_ADDRESS_BASE 0xC |
| #define | PCI_DATA_TAG ' ICP' |
| #define | PCI_DATA_VERSION 1 |
| #define | PCI_BUS_INTERFACE_STANDARD_VERSION 1 |
| #define | PCI_DEVICE_PRESENT_INTERFACE_VERSION 1 |
| #define | PCI_USE_SUBSYSTEM_IDS 0x00000001 |
| #define | PCI_USE_REVISION 0x00000002 |
Typedefs |
| typedef _PCI_SLOT_NUMBER | PCI_SLOT_NUMBER |
| typedef _PCI_SLOT_NUMBER * | PPCI_SLOT_NUMBER |
| typedef _PCI_COMMON_CONFIG | PCI_COMMON_CONFIG |
| typedef _PCI_COMMON_CONFIG * | PPCI_COMMON_CONFIG |
| typedef _PCI_CAPABILITIES_HEADER | PCI_CAPABILITIES_HEADER |
| typedef _PCI_CAPABILITIES_HEADER * | PPCI_CAPABILITIES_HEADER |
| typedef _PCI_PMC | PCI_PMC |
| typedef _PCI_PMC * | PPCI_PMC |
| typedef _PCI_PMCSR | PCI_PMCSR |
| typedef _PCI_PMCSR * | PPCI_PMCSR |
| typedef _PCI_PMCSR_BSE | PCI_PMCSR_BSE |
| typedef _PCI_PMCSR_BSE * | PPCI_PMCSR_BSE |
| typedef _PCI_PM_CAPABILITY | PCI_PM_CAPABILITY |
| typedef _PCI_PM_CAPABILITY * | PPCI_PM_CAPABILITY |
| typedef _PCI_AGP_CAPABILITY | PCI_AGP_CAPABILITY |
| typedef _PCI_AGP_CAPABILITY * | PPCI_AGP_CAPABILITY |
| typedef _PCI_MSI_CAPABILITY | PCI_MSI_CAPABILITY |
| typedef _PCI_MSI_CAPABILITY * | PPCI_PCI_CAPABILITY |
| typedef _PCI_REGISTRY_INFO | PCI_REGISTRY_INFO |
| typedef _PCI_REGISTRY_INFO * | PPCI_REGISTRY_INFO |
| typedef _PCI_TYPE1_CFG_BITS | PCI_TYPE1_CFG_BITS |
| typedef _PCI_TYPE1_CFG_BITS * | PPCI_TYPE1_CFG_BITS |
| typedef _PCI_TYPE2_CSE_BITS | PCI_TYPE2_CSE_BITS |
| typedef _PCI_TYPE2_CSE_BITS | PPCI_TYPE2_CSE_BITS |
| typedef _PCI_TYPE2_ADDRESS_BITS | PCI_TYPE2_ADDRESS_BITS |
| typedef _PCI_TYPE2_ADDRESS_BITS * | PPCI_TYPE2_ADDRESS_BITS |
| typedef _PCI_TYPE0_CFG_CYCLE_BITS | PCI_TYPE0_CFG_CYCLE_BITS |
| typedef _PCI_TYPE0_CFG_CYCLE_BITS * | PPCI_TYPE0_CFG_CYCLE_BITS |
| typedef _PCI_TYPE1_CFG_CYCLE_BITS | PCI_TYPE1_CFG_CYCLE_BITS |
| typedef _PCI_TYPE1_CFG_CYCLE_BITS * | PPCI_TYPE1_CFG_CYCLE_BITS |
| typedef VOID(* | PciPin2Line )(IN struct _BUS_HANDLER *BusHandler, IN struct _BUS_HANDLER *RootHandler, IN PCI_SLOT_NUMBER SlotNumber, IN PPCI_COMMON_CONFIG PciData) |
| typedef VOID(* | PciLine2Pin )(IN struct _BUS_HANDLER *BusHandler, IN struct _BUS_HANDLER *RootHandler, IN PCI_SLOT_NUMBER SlotNumber, IN PPCI_COMMON_CONFIG PciNewData, IN PPCI_COMMON_CONFIG PciOldData) |
| typedef VOID(* | PciReadWriteConfig )(IN struct _BUS_HANDLER *BusHandler, IN PCI_SLOT_NUMBER Slot, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length) |
| typedef _PCIBUSDATA | PCIBUSDATA |
| typedef _PCIBUSDATA * | PPCIBUSDATA |
| typedef ULONG(* | PCI_READ_WRITE_CONFIG )(IN PVOID Context, IN UCHAR BusOffset, IN ULONG Slot, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length) |
| typedef VOID(* | PCI_PIN_TO_LINE )(IN PVOID Context, IN PPCI_COMMON_CONFIG PciData) |
| typedef VOID(* | PCI_LINE_TO_PIN )(IN PVOID Context, IN PPCI_COMMON_CONFIG PciNewData, IN PPCI_COMMON_CONFIG PciOldData) |
| typedef _PCI_BUS_INTERFACE_STANDARD | PCI_BUS_INTERFACE_STANDARD |
| typedef _PCI_BUS_INTERFACE_STANDARD * | PPCI_BUS_INTERFACE_STANDARD |
| typedef BOOLEAN(* | PPCI_IS_DEVICE_PRESENT )(IN USHORT VendorID, IN USHORT DeviceID, IN UCHAR RevisionID, IN USHORT SubVendorID, IN USHORT SubSystemID, IN ULONG Flags) |
| typedef _PCI_DEVICE_PRESENT_INTERFACE | PCI_DEVICE_PRESENT_INTERFACE |
| typedef _PCI_DEVICE_PRESENT_INTERFACE * | PPCI_DEVICE_PRESENT_INTERFACE |
