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#include <stdarg.h>
00007
#include "ki.h"
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#include "fedefs.h"
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00010
00011
#ifndef IN_KERNEL
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extern void RaiseException ();
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#endif
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00015
#include <assert.h>
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#include <stdarg.h>
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#include <stddef.h>
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#ifndef unix
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#include <string.h>
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#endif
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00022
00023
00024
00025
00026
#include "fepublic.h"
00027
#include "fehelper.h"
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#include "fesupprt.h"
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00030
void fp82_default_fp_exception_fault(
void *ps, EM_uint_t isrcode);
00031
void fp82_default_fp_exception_trap(
void *ps, EM_uint_t isr_code);
00032
00033 #define RESTORE_CONSTANTS { \
00034
FR[0] = FP_ZERO; \
00035
FR[1] = FP_ONE; \
00036
PR[0] = 1; \
00037
GR[0].value = 0; \
00038
GR[0].nat = 0; \
00039
}
00040
00041
00042
00043
00044
00045
void
00046 GETSTATE_F1(
00047 EM_pred_reg_specifier Pr0,
00048 EM_fp_reg_specifier Fr1,
00049 EM_fp_reg_specifier Fr3,
00050 EM_fp_reg_specifier Fr4,
00051 EM_fp_reg_specifier Fr2) {
00052
00053 }
00054
00055
void
00056 PUTSTATE_F1(
00057 EM_fp_reg_specifier Fr1) {
00058
00059
RESTORE_CONSTANTS;
00060 }
00061
00062
00063
00064
00065
void
00066 GETSTATE_F4(
00067 EM_pred_reg_specifier Pr0,
00068 EM_pred_reg_specifier Pr1,
00069 EM_pred_reg_specifier Pr2,
00070 EM_fp_reg_specifier Fr2,
00071 EM_fp_reg_specifier Fr3) {
00072 }
00073
00074
void
00075 PUTSTATE_F4(
00076 EM_pred_reg_specifier Pr1,
00077 EM_pred_reg_specifier Pr2) {
00078
00079
RESTORE_CONSTANTS;
00080 }
00081
00082
00083
00084
00085
void
00086 GETSTATE_F6(
00087 EM_pred_reg_specifier Pr0,
00088 EM_fp_reg_specifier Fr1,
00089 EM_pred_reg_specifier Pr2,
00090 EM_fp_reg_specifier Fr2,
00091 EM_fp_reg_specifier Fr3) {
00092 }
00093
00094
void
00095 PUTSTATE_F6(
00096 EM_fp_reg_specifier Fr1,
00097 EM_pred_reg_specifier Pr2) {
00098
00099
RESTORE_CONSTANTS;
00100 }
00101
00102
00103
00104
00105
00106
void
00107 GETSTATE_F7(
00108 EM_pred_reg_specifier Pr0,
00109 EM_fp_reg_specifier Fr1,
00110 EM_pred_reg_specifier Pr2,
00111 EM_fp_reg_specifier Fr3) {
00112 }
00113
00114
00115
void
00116 PUTSTATE_F7(
00117 EM_fp_reg_specifier Fr1,
00118 EM_pred_reg_specifier Pr2) {
00119
00120
RESTORE_CONSTANTS;
00121 }
00122
00123
00124
00125
00126
void
00127 GETSTATE_F8(
00128 EM_pred_reg_specifier Pr0,
00129 EM_fp_reg_specifier Fr1,
00130 EM_fp_reg_specifier Fr2,
00131 EM_fp_reg_specifier Fr3) {
00132 }
00133
00134
void
00135 PUTSTATE_F8(
00136 EM_fp_reg_specifier Fr1) {
00137
00138
RESTORE_CONSTANTS;
00139 }
00140
00141
00142
00143
00144
void
00145 GETSTATE_F10(
00146 EM_pred_reg_specifier Pr0,
00147 EM_fp_reg_specifier Fr1,
00148 EM_fp_reg_specifier Fr2) {
00149
00150
SIGNED_FORM = 0;
00151
TRUNC_FORM = 0;
00152
UNSIGNED_FORM = 0;
00153 }
00154
00155
void
00156 PUTSTATE_F10(
00157 EM_fp_reg_specifier Fr1) {
00158
00159
RESTORE_CONSTANTS;
00160 }
00161
00162
00163 void fp82_default_fp_exception_fault(
void *vps, EM_uint_t isr_code) {
00164
EM_state_type *ps;
00165 ps = (
EM_state_type *)vps;
00166 ps->
state_MERCED_RTL &= ~0xffff0000;
00167 ps->
state_MERCED_RTL |= (isr_code << 16);
00168 ps->
trap_type = 1;
00169 }
00170
00171
00172 void fp82_default_fp_exception_trap(
void *vps, EM_uint_t isr_code) {
00173
EM_state_type *ps;
00174 ps = (
EM_state_type *)vps;
00175 ps->
state_MERCED_RTL &= ~0xffff0000;
00176 ps->
state_MERCED_RTL |= (isr_code << 16);
00177 ps->
trap_type = 0;
00178 }
00179
00180
00181
00182
00183
00184
void
00185 fp82_EM_initialize_state(
EM_state_type *ps) {
00186
EM_int_t i;
00187
00188
PSR.be = 0;
00189
PSR.dfl = 0;
00190
PSR.dfh = 0;
00191
PSR.mfl = 0;
00192
PSR.mfh = 0;
00193
00194
FPSR.traps_vd = 1;
00195
FPSR.traps_dd = 1;
00196
FPSR.traps_zd = 1;
00197
FPSR.traps_od = 1;
00198
FPSR.traps_ud = 1;
00199
FPSR.traps_id = 1;
00200
00201
FPSR.sf0_controls_ftz = 0;
00202
FPSR.sf0_controls_wre = 1;
00203
FPSR.sf0_controls_pc =
sf_double_extended;
00204
FPSR.sf0_controls_rc =
rc_rn;
00205
FPSR.sf0_controls_td = 0;
00206
FPSR.sf0_flags_v = 0;
00207
FPSR.sf0_flags_d = 0;
00208
FPSR.sf0_flags_z = 0;
00209
FPSR.sf0_flags_o = 0;
00210
FPSR.sf0_flags_u = 0;
00211
FPSR.sf0_flags_i = 0;
00212
00213
FPSR.sf1_controls_ftz = 0;
00214
FPSR.sf1_controls_wre = 1;
00215
FPSR.sf1_controls_pc =
sf_double_extended;
00216
FPSR.sf1_controls_rc =
rc_rn;
00217
FPSR.sf1_controls_td = 0;
00218
FPSR.sf1_flags_v = 0;
00219
FPSR.sf1_flags_d = 0;
00220
FPSR.sf1_flags_z = 0;
00221
FPSR.sf1_flags_o = 0;
00222
FPSR.sf1_flags_u = 0;
00223
FPSR.sf1_flags_i = 0;
00224
00225
FPSR.sf2_controls_ftz = 0;
00226
FPSR.sf2_controls_wre = 1;
00227
FPSR.sf2_controls_pc =
sf_double_extended;
00228
FPSR.sf2_controls_rc =
rc_rn;
00229
FPSR.sf2_controls_td = 0;
00230
FPSR.sf2_flags_v = 0;
00231
FPSR.sf2_flags_d = 0;
00232
FPSR.sf2_flags_z = 0;
00233
FPSR.sf2_flags_o = 0;
00234
FPSR.sf2_flags_u = 0;
00235
FPSR.sf2_flags_i = 0;
00236
00237
FPSR.sf3_controls_ftz = 0;
00238
FPSR.sf3_controls_wre = 1;
00239
FPSR.sf3_controls_pc =
sf_double_extended;
00240
FPSR.sf3_controls_rc =
rc_rn;
00241
FPSR.sf3_controls_td = 0;
00242
FPSR.sf3_flags_v = 0;
00243
FPSR.sf3_flags_d = 0;
00244
FPSR.sf3_flags_z = 0;
00245
FPSR.sf3_flags_o = 0;
00246
FPSR.sf3_flags_u = 0;
00247
FPSR.sf3_flags_i = 0;
00248
FPSR.reserved = 0;
00249
00250
PR[0] = 1;
00251
for (i=1;i<
EM_NUM_PR;i++)
00252
PR[i] = 0;
00253
00254 ps->
state_MERCED_RTL = 0;
00255
00256
FR[0] = FP_ZERO;
00257
FR[1] = FP_ONE;
00258
00259
for (i=2;i<
MAX_REAL_FR_INDEX;i++)
00260
FR[i] = FP_ZERO;
00261
00262
for (i=0;i<
MAX_REAL_GR_INDEX;i++) {
00263
GR[i].value = 0;
00264
GR[i].nat = 0;
00265 }
00266
00267 ps->
state_fp82_fp_exception_fault =
fp82_default_fp_exception_fault;
00268 ps->
state_fp82_fp_exception_trap =
fp82_default_fp_exception_trap;
00269 }
00270
00271
00272
00273
00274
EM_boolean_t
00275 fp82_fp_software_assistance_required(
EM_state_type *ps,
00276 EM_opcode_type calling_instruction, ...)
00277 {
00278
return(0);
00279 }
00280
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00282
00283
INLINE void
00284 disabled_fp_register_fault(EM_uint_t isr_code, EM_uint_t itype)
00285 {
00286
#ifdef IN_KERNEL
00287
FP_EMULATION_ERROR0 (
"disabled_fp_register_fault () Internal Error\n");
00288
#else
00289
printf (
"disabled_fp_register_fault () Internal Error\n");
00290
exit (1);
00291
#endif
00292
}
00293
00294
00295
INLINE void
00296 fp_exception_fault(EM_uint_t isr_code)
00297 {
00298
00299
PR[0] = 1;
00300
GR[0].value = 0;
00301
GR[0].nat = 0;
00302
FR[0] = FP_ZERO;
00303
FR[1] = FP_ONE;
00304
00305 ps->state_fp82_fp_exception_fault((
EM_state_type *)ps, isr_code);
00306
00307 }
00308
00309
INLINE void
00310 fp_exception_trap(EM_uint_t isr_code)
00311 {
00312
00313 isr_code |= 0x00000001;
00314
00315 ps->state_fp82_fp_exception_trap((
EM_state_type *)ps, isr_code);
00316
00317 }
00318
00319
00320
INLINE void
00321 illegal_operation_fault(EM_uint_t non_rs)
00322 {
00323
#ifdef IN_KERNEL
00324
FP_EMULATION_ERROR0 (
"illegal_operation_fault () Internal Error\n");
00325
#else
00326
printf (
"illegal_operation_fault () Internal Error\n");
00327
exit (1);
00328
#endif
00329
}
00330
00331
INLINE void
00332 check_target_register(EM_uint_t reg_specifier, EM_uint_t itype)
00333 {
00334
if(reg_specifier == 0) {
00335
#ifdef IN_KERNEL
00336
FP_EMULATION_ERROR0 (
"fp_check_target_register () Internal Error\n");
00337
#else
00338
printf (
"fp_check_target_register () Internal Error\n");
00339
exit (1);
00340
#endif
00341
}
00342 }
00343
00344
void
00345 fp_check_target_register(EM_uint_t reg_specifier)
00346 {
00347
if( (reg_specifier == 0) || (reg_specifier == 1) ){
00348
#ifdef IN_KERNEL
00349
FP_EMULATION_ERROR0 (
"fp_check_target_register () Internal Error\n")
00350 #
else
00351 printf (
"fp_check_target_register () Internal Error\n");
00352
exit (1);
00353
#endif
00354
}
00355 }
00356
00357
00358
INLINE void
00359 reserved_register_field_fault(EM_uint_t val)
00360 {
00361
#ifdef IN_KERNEL
00362
FP_EMULATION_ERROR0 (
"reserved_register_field_fault () Internal Error\n")
00363 #
else
00364 printf (
"reserved_register_field_fault () Internal Error\n");
00365
exit (1);
00366
#endif
00367
}
00368
00369