test: feinstr.c Source File

00001 // ****************************** 00002 // Intel Confidential 00003 // ****************************** 00004 00005 // ****************************** 00006 // asm mappings to instructions 00007 // ****************************** 00008 00009 // MACH 00010 #include "ki.h" 00011 00012 #ifndef _STDIO_H 00013 #include <stdio.h> 00014 #endif 00015 00016 #include "fepublic.h" 00017 #include "fehelper.h" 00018 #include "festate.h" 00019 #include "feinstr.h" 00020 00021 00022 // ****************************************************************** 00023 // Public functions 00024 // ****************************************************************** 00025 00026 // ****************************************************************** 00027 // fma: Floating point multiply add 00028 // ****************************************************************** 00029 void 00030 fp82_fma(EM_state_type *ps, 00031 EM_opcode_pc_type pc, 00032 EM_opcode_sf_type sf, 00033 EM_pred_reg_specifier qp, 00034 EM_fp_reg_specifier f1, 00035 EM_fp_reg_specifier f3, 00036 EM_fp_reg_specifier f4, 00037 EM_fp_reg_specifier f2) 00038 { 00039 GETSTATE_F1(qp,f1,f3,f4,f2); 00040 _fma(ps, pc, sf, qp, f1, f3, f4, f2); 00041 PUTSTATE_F1(f1); 00042 } 00043 00044 00045 // ****************************************************************** 00046 // fpma: Floating point parallel multiply add 00047 // ****************************************************************** 00048 void 00049 fp82_fpma(EM_state_type *ps, 00050 EM_opcode_sf_type sf, 00051 EM_pred_reg_specifier qp, 00052 EM_fp_reg_specifier f1, 00053 EM_fp_reg_specifier f3, 00054 EM_fp_reg_specifier f4, 00055 EM_fp_reg_specifier f2) 00056 { 00057 GETSTATE_F1(qp,f1,f3,f4,f2); 00058 _fpma(ps, sf, qp, f1, f3, f4, f2); 00059 PUTSTATE_F1(f1); 00060 } 00061 00062 // ****************************************************************** 00063 // Floating-point Multiply Subtract 00064 // ****************************************************************** 00065 void 00066 fp82_fms(EM_state_type *ps, 00067 EM_opcode_pc_type pc, 00068 EM_opcode_sf_type sf, 00069 EM_pred_reg_specifier qp, 00070 EM_fp_reg_specifier f1, 00071 EM_fp_reg_specifier f3, 00072 EM_fp_reg_specifier f4, 00073 EM_fp_reg_specifier f2) 00074 { 00075 GETSTATE_F1(qp,f1,f3,f4,f2); 00076 _fms(ps, pc, sf, qp, f1, f3, f4, f2); 00077 PUTSTATE_F1(f1); 00078 } 00079 00080 00081 // ****************************************************************** 00082 // Floating-point Parallel Multiply Subtract 00083 // ****************************************************************** 00084 void 00085 fp82_fpms(EM_state_type *ps, 00086 EM_opcode_sf_type sf, 00087 EM_pred_reg_specifier qp, 00088 EM_fp_reg_specifier f1, 00089 EM_fp_reg_specifier f3, 00090 EM_fp_reg_specifier f4, 00091 EM_fp_reg_specifier f2) 00092 { 00093 GETSTATE_F1(qp,f1,f3,f4,f2); 00094 _fpms(ps, sf, qp, f1, f3, f4, f2); 00095 PUTSTATE_F1(f1); 00096 } 00097 00098 00099 // ****************************************************************** 00100 // Floating-point Negative Multiply Add 00101 // ****************************************************************** 00102 void 00103 fp82_fnma(EM_state_type *ps, 00104 EM_opcode_pc_type pc, 00105 EM_opcode_sf_type sf, 00106 EM_pred_reg_specifier qp, 00107 EM_fp_reg_specifier f1, 00108 EM_fp_reg_specifier f3, 00109 EM_fp_reg_specifier f4, 00110 EM_fp_reg_specifier f2) 00111 { 00112 GETSTATE_F1(qp,f1,f3,f4,f2); 00113 _fnma(ps, pc, sf, qp, f1, f3, f4, f2); 00114 PUTSTATE_F1(f1); 00115 } 00116 00117 // ****************************************************************** 00118 // Floating-point Parallel Negative Multiply Add 00119 // ****************************************************************** 00120 void 00121 fp82_fpnma(EM_state_type *ps, 00122 EM_opcode_sf_type sf, 00123 EM_pred_reg_specifier qp, 00124 EM_fp_reg_specifier f1, 00125 EM_fp_reg_specifier f3, 00126 EM_fp_reg_specifier f4, 00127 EM_fp_reg_specifier f2) 00128 { 00129 GETSTATE_F1(qp,f1,f3,f4,f2); 00130 _fpnma(ps, sf, qp, f1, f3, f4, f2); 00131 PUTSTATE_F1(f1); 00132 } 00133 00134 00135 // ****************************************************************** 00136 // Floating-point Compare 00137 // ****************************************************************** 00138 void 00139 fp82_fcmp_eq(EM_state_type *ps, 00140 EM_opcode_ctype_type fctype, 00141 EM_opcode_sf_type sf, 00142 EM_pred_reg_specifier qp, 00143 EM_pred_reg_specifier p1, 00144 EM_pred_reg_specifier p2, 00145 EM_fp_reg_specifier f2, 00146 EM_fp_reg_specifier f3) 00147 { 00148 GETSTATE_F4(qp,p1,p2,f2,f3); 00149 _fcmp(ps, frelEQ, fctype, sf, (EM_uint_t)qp, 00150 (EM_uint_t)p1, (EM_uint_t)p2, (EM_uint_t)f2, (EM_uint_t)f3); 00151 PUTSTATE_F4(p1,p2); 00152 } 00153 00154 void 00155 fp82_fcmp_lt(EM_state_type *ps, 00156 EM_opcode_ctype_type fctype, 00157 EM_opcode_sf_type sf, 00158 EM_pred_reg_specifier qp, 00159 EM_pred_reg_specifier p1, 00160 EM_pred_reg_specifier p2, 00161 EM_fp_reg_specifier f2, 00162 EM_fp_reg_specifier f3) 00163 { 00164 GETSTATE_F4(qp,p1,p2,f2,f3); 00165 _fcmp(ps, frelLT, fctype, sf, (EM_uint_t)qp, 00166 (EM_uint_t)p1, (EM_uint_t)p2, (EM_uint_t)f2, (EM_uint_t)f3); 00167 PUTSTATE_F4(p1,p2); 00168 } 00169 00170 void 00171 fp82_fcmp_le(EM_state_type *ps, 00172 EM_opcode_ctype_type fctype, 00173 EM_opcode_sf_type sf, 00174 EM_pred_reg_specifier qp, 00175 EM_pred_reg_specifier p1, 00176 EM_pred_reg_specifier p2, 00177 EM_fp_reg_specifier f2, 00178 EM_fp_reg_specifier f3) 00179 { 00180 GETSTATE_F4(qp,p1,p2,f2,f3); 00181 _fcmp(ps, frelLE, fctype, sf, (EM_uint_t)qp, 00182 (EM_uint_t)p1, (EM_uint_t)p2, (EM_uint_t)f2, (EM_uint_t)f3); 00183 PUTSTATE_F4(p1,p2); 00184 } 00185 00186 void 00187 fp82_fcmp_unord(EM_state_type *ps, 00188 EM_opcode_ctype_type fctype, 00189 EM_opcode_sf_type sf, 00190 EM_pred_reg_specifier qp, 00191 EM_pred_reg_specifier p1, 00192 EM_pred_reg_specifier p2, 00193 EM_fp_reg_specifier f2, 00194 EM_fp_reg_specifier f3) 00195 { 00196 GETSTATE_F4(qp,p1,p2,f2,f3); 00197 _fcmp(ps, frelUNORD, fctype, sf, (EM_uint_t)qp, 00198 (EM_uint_t)p1, (EM_uint_t)p2, (EM_uint_t)f2, (EM_uint_t)f3); 00199 PUTSTATE_F4(p1,p2); 00200 } 00201 00202 00203 // ****************************************************************** 00204 // Floating-point Reciprocal Approximation 00205 // ****************************************************************** 00206 void 00207 fp82_frcpa(EM_state_type *ps, 00208 EM_opcode_sf_type sf, 00209 EM_pred_reg_specifier qp, 00210 EM_fp_reg_specifier f1, 00211 EM_pred_reg_specifier p2, 00212 EM_fp_reg_specifier f2, 00213 EM_fp_reg_specifier f3) 00214 { 00215 GETSTATE_F6(qp,f1,p2,f2,f3); 00216 _frcpa(ps, sf, qp, f1, p2, f2, f3); 00217 PUTSTATE_F6(f1,p2); 00218 } 00219 00220 // ****************************************************************** 00221 // Floating-point Parallel Reciprocal Approximation 00222 // ****************************************************************** 00223 void 00224 fp82_fprcpa(EM_state_type *ps, 00225 EM_opcode_sf_type sf, 00226 EM_pred_reg_specifier qp, 00227 EM_fp_reg_specifier f1, 00228 EM_pred_reg_specifier p2, 00229 EM_fp_reg_specifier f2, 00230 EM_fp_reg_specifier f3) 00231 { 00232 GETSTATE_F6(qp,f1,p2,f2,f3); 00233 _fprcpa(ps, sf, qp, f1, p2, f2, f3); 00234 PUTSTATE_F6(f1,p2); 00235 } 00236 00237 00238 // ****************************************************************** 00239 // Floating-point Reciprocal Square Root Approximation 00240 // ****************************************************************** 00241 00242 void 00243 fp82_frsqrta(EM_state_type *ps, 00244 EM_opcode_sf_type sf, 00245 EM_pred_reg_specifier qp, 00246 EM_fp_reg_specifier f1, 00247 EM_pred_reg_specifier p2, 00248 EM_fp_reg_specifier f3) 00249 { 00250 GETSTATE_F7(qp,f1,p2,f3); 00251 _frsqrta(ps, sf, qp, f1, p2, f3); 00252 PUTSTATE_F7(f1,p2); 00253 } 00254 00255 // ****************************************************************** 00256 // Floating-point Parallel Reciprocal Square Root Approximation 00257 // ****************************************************************** 00258 void 00259 fp82_fprsqrta(EM_state_type *ps, 00260 EM_opcode_sf_type sf, 00261 EM_pred_reg_specifier qp, 00262 EM_fp_reg_specifier f1, 00263 EM_pred_reg_specifier p2, 00264 EM_fp_reg_specifier f3) 00265 { 00266 GETSTATE_F7(qp,f1,p2,f3); 00267 _fprsqrta(ps, sf, qp, f1, p2, f3); 00268 PUTSTATE_F7(f1,p2); 00269 } 00270 00271 // ****************************************************************** 00272 // Floating-point Minimum 00273 // ****************************************************************** 00274 void 00275 fp82_fmin(EM_state_type *ps, 00276 EM_opcode_sf_type sf, 00277 EM_pred_reg_specifier qp, 00278 EM_fp_reg_specifier f1, 00279 EM_fp_reg_specifier f2, 00280 EM_fp_reg_specifier f3) 00281 { 00282 GETSTATE_F8(qp,f1,f2,f3); 00283 _fmin(ps, sf, qp, f1, f2, f3); 00284 PUTSTATE_F8(f1); 00285 } 00286 00287 // ****************************************************************** 00288 // Floating-point Maximum 00289 // ****************************************************************** 00290 void 00291 fp82_fmax(EM_state_type *ps, 00292 EM_opcode_sf_type sf, 00293 EM_pred_reg_specifier qp, 00294 EM_fp_reg_specifier f1, 00295 EM_fp_reg_specifier f2, 00296 EM_fp_reg_specifier f3) 00297 { 00298 GETSTATE_F8(qp,f1,f2,f3); 00299 _fmax(ps, sf, qp, f1, f2, f3); 00300 PUTSTATE_F8(f1); 00301 } 00302 00303 // ****************************************************************** 00304 // Floating-point Absolute Minimum 00305 // ****************************************************************** 00306 void 00307 fp82_famin(EM_state_type *ps, 00308 EM_opcode_sf_type sf, 00309 EM_pred_reg_specifier qp, 00310 EM_fp_reg_specifier f1, 00311 EM_fp_reg_specifier f2, 00312 EM_fp_reg_specifier f3) 00313 { 00314 GETSTATE_F8(qp,f1,f2,f3); 00315 _famin(ps, sf, (EM_uint_t)qp, (EM_uint_t)f1, (EM_uint_t)f2, (EM_uint_t)f3); 00316 PUTSTATE_F8(f1); 00317 } 00318 00319 // ****************************************************************** 00320 // Floating-point Absolute Maximum 00321 // ****************************************************************** 00322 void 00323 fp82_famax(EM_state_type *ps, 00324 EM_opcode_sf_type sf, 00325 EM_pred_reg_specifier qp, 00326 EM_fp_reg_specifier f1, 00327 EM_fp_reg_specifier f2, 00328 EM_fp_reg_specifier f3) 00329 { 00330 GETSTATE_F8(qp,f1,f2,f3); 00331 _famax(ps, sf, (EM_uint_t)qp, (EM_uint_t)f1, (EM_uint_t)f2, (EM_uint_t)f3); 00332 PUTSTATE_F8(f1); 00333 } 00334 00335 00336 // ****************************************************************** 00337 // Floating-point Parallel Minimum 00338 // ****************************************************************** 00339 void 00340 fp82_fpmin(EM_state_type *ps, 00341 EM_opcode_sf_type sf, 00342 EM_pred_reg_specifier qp, 00343 EM_fp_reg_specifier f1, 00344 EM_fp_reg_specifier f2, 00345 EM_fp_reg_specifier f3) 00346 { 00347 GETSTATE_F8(qp,f1,f2,f3); 00348 _fpmin(ps, sf, qp, f1, f2, f3); 00349 PUTSTATE_F8(f1); 00350 } 00351 00352 00353 // ****************************************************************** 00354 // Floating-point Parallel Maximum 00355 // ****************************************************************** 00356 void 00357 fp82_fpmax(EM_state_type *ps, 00358 EM_opcode_sf_type sf, 00359 EM_pred_reg_specifier qp, 00360 EM_fp_reg_specifier f1, 00361 EM_fp_reg_specifier f2, 00362 EM_fp_reg_specifier f3) 00363 { 00364 GETSTATE_F8(qp,f1,f2,f3); 00365 _fpmax(ps, sf, qp, f1, f2, f3); 00366 PUTSTATE_F8(f1); 00367 } 00368 00369 // ****************************************************************** 00370 // Floating-point Parallel Absolute Minimum 00371 // ****************************************************************** 00372 void 00373 fp82_fpamin(EM_state_type *ps, 00374 EM_opcode_sf_type sf, 00375 EM_pred_reg_specifier qp, 00376 EM_fp_reg_specifier f1, 00377 EM_fp_reg_specifier f2, 00378 EM_fp_reg_specifier f3) 00379 { 00380 GETSTATE_F8(qp,f1,f2,f3); 00381 _fpamin(ps, sf, (EM_uint_t)qp, (EM_uint_t)f1, (EM_uint_t)f2, (EM_uint_t)f3); 00382 PUTSTATE_F8(f1); 00383 } 00384 00385 00386 // ****************************************************************** 00387 // Floating-point Parallel Absolute Maximum 00388 // ****************************************************************** 00389 void 00390 fp82_fpamax(EM_state_type *ps, 00391 EM_opcode_sf_type sf, 00392 EM_pred_reg_specifier qp, 00393 EM_fp_reg_specifier f1, 00394 EM_fp_reg_specifier f2, 00395 EM_fp_reg_specifier f3) 00396 { 00397 GETSTATE_F8(qp,f1,f2,f3); 00398 _fpamax(ps, sf, (EM_uint_t)qp, (EM_uint_t)f1, (EM_uint_t)f2, (EM_uint_t)f3); 00399 PUTSTATE_F8(f1); 00400 } 00401 00402 00403 // ****************************************************************** 00404 // Floating-point Parallel Compare 00405 // ****************************************************************** 00406 void 00407 fp82_fpcmp_eq(EM_state_type *ps, 00408 EM_opcode_sf_type sf, 00409 EM_pred_reg_specifier qp, 00410 EM_fp_reg_specifier f1, 00411 EM_fp_reg_specifier f2, 00412 EM_fp_reg_specifier f3) 00413 { 00414 GETSTATE_F8(qp,f1,f2,f3); 00415 _fpcmp(ps, frelEQ, sf, (EM_uint_t)qp, 00416 (EM_uint_t)f1, (EM_uint_t)f2, (EM_uint_t)f3); 00417 PUTSTATE_F8(f1); 00418 } 00419 00420 00421 void 00422 fp82_fpcmp_lt(EM_state_type *ps, 00423 EM_opcode_sf_type sf, 00424 EM_pred_reg_specifier qp, 00425 EM_fp_reg_specifier f1, 00426 EM_fp_reg_specifier f2, 00427 EM_fp_reg_specifier f3) 00428 { 00429 GETSTATE_F8(qp,f1,f2,f3); 00430 _fpcmp(ps, frelLT, sf, (EM_uint_t)qp, 00431 (EM_uint_t)f1, (EM_uint_t)f2, (EM_uint_t)f3); 00432 PUTSTATE_F8(f1); 00433 } 00434 00435 void 00436 fp82_fpcmp_le(EM_state_type *ps, 00437 EM_opcode_sf_type sf, 00438 EM_pred_reg_specifier qp, 00439 EM_fp_reg_specifier f1, 00440 EM_fp_reg_specifier f2, 00441 EM_fp_reg_specifier f3) 00442 { 00443 GETSTATE_F8(qp,f1,f2,f3); 00444 _fpcmp(ps, frelLE, sf, (EM_uint_t)qp, 00445 (EM_uint_t)f1, (EM_uint_t)f2, (EM_uint_t)f3); 00446 PUTSTATE_F8(f1); 00447 } 00448 00449 void 00450 fp82_fpcmp_unord(EM_state_type *ps, 00451 EM_opcode_sf_type sf, 00452 EM_pred_reg_specifier qp, 00453 EM_fp_reg_specifier f1, 00454 EM_fp_reg_specifier f2, 00455 EM_fp_reg_specifier f3) 00456 { 00457 GETSTATE_F8(qp,f1,f2,f3); 00458 _fpcmp(ps, frelUNORD, sf, (EM_uint_t)qp, 00459 (EM_uint_t)f1, (EM_uint_t)f2, (EM_uint_t)f3); 00460 PUTSTATE_F8(f1); 00461 } 00462 00463 void 00464 fp82_fpcmp_neq(EM_state_type *ps, 00465 EM_opcode_sf_type sf, 00466 EM_pred_reg_specifier qp, 00467 EM_fp_reg_specifier f1, 00468 EM_fp_reg_specifier f2, 00469 EM_fp_reg_specifier f3) 00470 { 00471 GETSTATE_F8(qp,f1,f2,f3); 00472 _fpcmp(ps, 00473 frelNEQ, sf, (EM_uint_t)qp, 00474 (EM_uint_t)f1, (EM_uint_t)f2, (EM_uint_t)f3); 00475 PUTSTATE_F8(f1); 00476 } 00477 00478 void 00479 fp82_fpcmp_nlt(EM_state_type *ps, 00480 EM_opcode_sf_type sf, 00481 EM_pred_reg_specifier qp, 00482 EM_fp_reg_specifier f1, 00483 EM_fp_reg_specifier f2, 00484 EM_fp_reg_specifier f3) 00485 { 00486 GETSTATE_F8(qp,f1,f2,f3); 00487 _fpcmp(ps, frelNLT, sf, (EM_uint_t)qp, 00488 (EM_uint_t)f1, (EM_uint_t)f2, (EM_uint_t)f3); 00489 PUTSTATE_F8(f1); 00490 } 00491 00492 void 00493 fp82_fpcmp_nle(EM_state_type *ps, 00494 EM_opcode_sf_type sf, 00495 EM_pred_reg_specifier qp, 00496 EM_fp_reg_specifier f1, 00497 EM_fp_reg_specifier f2, 00498 EM_fp_reg_specifier f3) 00499 { 00500 GETSTATE_F8(qp,f1,f2,f3); 00501 _fpcmp(ps, frelNLE, sf, (EM_uint_t)qp, 00502 (EM_uint_t)f1, (EM_uint_t)f2, (EM_uint_t)f3); 00503 PUTSTATE_F8(f1); 00504 } 00505 00506 void 00507 fp82_fpcmp_ord(EM_state_type *ps, 00508 EM_opcode_sf_type sf, 00509 EM_pred_reg_specifier qp, 00510 EM_fp_reg_specifier f1, 00511 EM_fp_reg_specifier f2, 00512 EM_fp_reg_specifier f3) 00513 { 00514 GETSTATE_F8(qp,f1,f2,f3); 00515 _fpcmp(ps, frelORD, sf, (EM_uint_t)qp, 00516 (EM_uint_t)f1, (EM_uint_t)f2, (EM_uint_t)f3); 00517 PUTSTATE_F8(f1); 00518 } 00519 00520 // ****************************************************************** 00521 // Convert Floating-point to Integer 00522 // ****************************************************************** 00523 void 00524 fp82_fcvt_fx(EM_state_type *ps, 00525 EM_opcode_sf_type sf, 00526 EM_pred_reg_specifier qp, 00527 EM_fp_reg_specifier f1, 00528 EM_fp_reg_specifier f2) 00529 { 00530 GETSTATE_F10(qp,f1,f2); 00531 SIGNED_FORM = 1; 00532 _fcvt_fx(ps, sf, (EM_uint_t)qp, (EM_uint_t)f1, (EM_uint_t)f2); 00533 PUTSTATE_F10(f1); 00534 } 00535 00536 void 00537 fp82_fcvt_fxu(EM_state_type *ps, 00538 EM_opcode_sf_type sf, 00539 EM_pred_reg_specifier qp, 00540 EM_fp_reg_specifier f1, 00541 EM_fp_reg_specifier f2) 00542 { 00543 GETSTATE_F10(qp,f1,f2); 00544 UNSIGNED_FORM = 1; 00545 _fcvt_fx(ps, sf, (EM_uint_t)qp, (EM_uint_t)f1, (EM_uint_t)f2); 00546 PUTSTATE_F10(f1); 00547 } 00548 00549 00550 void 00551 fp82_fcvt_fx_trunc(EM_state_type *ps, 00552 EM_opcode_sf_type sf, 00553 EM_pred_reg_specifier qp, 00554 EM_fp_reg_specifier f1, 00555 EM_fp_reg_specifier f2) 00556 { 00557 00558 GETSTATE_F10(qp,f1,f2); 00559 SIGNED_FORM = 1; 00560 TRUNC_FORM = 1; 00561 _fcvt_fx(ps, sf, (EM_uint_t)qp, (EM_uint_t)f1, (EM_uint_t)f2); 00562 PUTSTATE_F10(f1); 00563 } 00564 00565 00566 void 00567 fp82_fcvt_fxu_trunc(EM_state_type *ps, 00568 EM_opcode_sf_type sf, 00569 EM_pred_reg_specifier qp, 00570 EM_fp_reg_specifier f1, 00571 EM_fp_reg_specifier f2) 00572 { 00573 GETSTATE_F10(qp,f1,f2); 00574 TRUNC_FORM = 1; 00575 UNSIGNED_FORM = 1; 00576 _fcvt_fx(ps, sf, (EM_uint_t)qp, (EM_uint_t)f1, (EM_uint_t)f2); 00577 PUTSTATE_F10(f1); 00578 } 00579 00580 00581 // ****************************************************************** 00582 // Parallel Convert Floating-point to Integer 00583 // ****************************************************************** 00584 void 00585 fp82_fpcvt_fx(EM_state_type *ps, 00586 EM_opcode_sf_type sf, 00587 EM_pred_reg_specifier qp, 00588 EM_fp_reg_specifier f1, 00589 EM_fp_reg_specifier f2) 00590 { 00591 GETSTATE_F10(qp,f1,f2); 00592 SIGNED_FORM = 1; 00593 _fpcvt_fx(ps, sf, (EM_uint_t)qp, (EM_uint_t)f1, (EM_uint_t)f2); 00594 PUTSTATE_F10(f1); 00595 } 00596 00597 00598 void 00599 fp82_fpcvt_fxu(EM_state_type *ps, 00600 EM_opcode_sf_type sf, 00601 EM_pred_reg_specifier qp, 00602 EM_fp_reg_specifier f1, 00603 EM_fp_reg_specifier f2) 00604 { 00605 GETSTATE_F10(qp,f1,f2); 00606 UNSIGNED_FORM = 1; 00607 _fpcvt_fx(ps, sf, (EM_uint_t)qp, (EM_uint_t)f1, (EM_uint_t)f2); 00608 PUTSTATE_F10(f1); 00609 } 00610 00611 void 00612 fp82_fpcvt_fx_trunc(EM_state_type *ps, 00613 EM_opcode_sf_type sf, 00614 EM_pred_reg_specifier qp, 00615 EM_fp_reg_specifier f1, 00616 EM_fp_reg_specifier f2) 00617 { 00618 00619 GETSTATE_F10(qp,f1,f2); 00620 SIGNED_FORM = 1; 00621 TRUNC_FORM = 1; 00622 _fpcvt_fx(ps, sf, (EM_uint_t)qp, (EM_uint_t)f1, (EM_uint_t)f2); 00623 PUTSTATE_F10(f1); 00624 } 00625 00626 void 00627 fp82_fpcvt_fxu_trunc(EM_state_type *ps, 00628 EM_opcode_sf_type sf, 00629 EM_pred_reg_specifier qp, 00630 EM_fp_reg_specifier f1, 00631 EM_fp_reg_specifier f2) 00632 { 00633 GETSTATE_F10(qp,f1,f2); 00634 TRUNC_FORM = 1; 00635 UNSIGNED_FORM = 1; 00636 _fpcvt_fx(ps, sf, (EM_uint_t)qp, (EM_uint_t)f1, (EM_uint_t)f2); 00637 PUTSTATE_F10(f1); 00638 } 00639 00640 //*************************************************************** 00641 // Instruction pages: The Underbar Routines 00642 //*************************************************************** 00643 00644 // ****************************************************************** 00645 // _fma 00646 // ****************************************************************** 00647 static INLINE void 00648 _fma(EM_state_type *ps, 00649 EM_opcode_pc_type pc, 00650 EM_opcode_sf_type sf, 00651 EM_uint_t qp, 00652 EM_uint_t f1, 00653 EM_uint_t f3, 00654 EM_uint_t f4, 00655 EM_uint_t f2) 00656 { 00657 EM_uint_t tmp_isrcode; 00658 EM_fp_reg_type tmp_default_result; 00659 EM_tmp_fp_env_type tmp_fp_env; 00660 EM_fp_dp_type tmp_res; 00661 00662 /* EAS START */ 00663 if (PR[qp]) { 00664 fp_check_target_register(f1); 00665 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, f4)) 00666 disabled_fp_register_fault(tmp_isrcode,0); 00667 00668 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3]) || fp_is_natval(FR[f4])) { 00669 FR[f1] = NATVAL; 00670 fp_update_psr(f1); 00671 } else { 00672 tmp_default_result = fma_exception_fault_check(f2, f3, f4, 00673 pc, sf, &tmp_fp_env); 00674 if (fp_raise_fault(tmp_fp_env)) { 00675 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 00676 return; // MACH 00677 } 00678 00679 if (fp_is_nan_or_inf(tmp_default_result)) { 00680 FR[f1] = tmp_default_result; 00681 } else { 00682 tmp_res = fp_mul(fp_reg_read(FR[f3]), 00683 fp_reg_read(FR[f4])); 00684 if (f2 != 0) 00685 tmp_res = fp_add(tmp_res, fp_reg_read(FR[f2]), tmp_fp_env); 00686 FR[f1] = fp_ieee_round(tmp_res, &tmp_fp_env); 00687 } 00688 00689 fp_update_fpsr(sf, tmp_fp_env); 00690 fp_update_psr(f1); 00691 if (fp_raise_traps(tmp_fp_env)) 00692 fp_exception_trap(fp_decode_trap(tmp_fp_env)); 00693 } 00694 } 00695 /* EAS END */ 00696 } 00697 00698 00699 // ****************************************************************** 00700 // _fpma 00701 // ****************************************************************** 00702 static INLINE void 00703 _fpma(EM_state_type *ps, 00704 EM_opcode_sf_type sf, 00705 EM_uint_t qp, 00706 EM_uint_t f1, 00707 EM_uint_t f3, 00708 EM_uint_t f4, 00709 EM_uint_t f2) 00710 { 00711 EM_uint_t tmp_isrcode, tmp_res_hi, tmp_res_lo; 00712 EM_pair_fp_reg_type tmp_default_result_pair; 00713 EM_tmp_fp_env_type tmp_fp_env; 00714 EM_fp_dp_type tmp_res; 00715 00716 /* EAS START */ 00717 if (PR[qp]) { 00718 fp_check_target_register(f1); 00719 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, f4)) 00720 disabled_fp_register_fault(tmp_isrcode,0); 00721 00722 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3]) || fp_is_natval(FR[f4])) { 00723 FR[f1] = NATVAL; 00724 fp_update_psr(f1); 00725 } else { 00726 tmp_default_result_pair = fpma_exception_fault_check(f2, 00727 f3, f4, sf, &tmp_fp_env); 00728 00729 if (fp_raise_fault(tmp_fp_env)) { 00730 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 00731 return; // MACH 00732 } 00733 00734 if (fp_is_nan_or_inf(tmp_default_result_pair.hi)) { 00735 tmp_res_hi = fp_single(tmp_default_result_pair.hi); 00736 } else { 00737 tmp_res = fp_mul(fp_reg_read_hi(f3), fp_reg_read_hi(f4)); 00738 if (f2 != 0) 00739 tmp_res = fp_add(tmp_res, fp_reg_read_hi(f2), tmp_fp_env); 00740 tmp_res_hi = fp_ieee_round_sp(tmp_res, high, &tmp_fp_env); 00741 } 00742 00743 if (fp_is_nan_or_inf(tmp_default_result_pair.lo)) { 00744 tmp_res_lo = fp_single(tmp_default_result_pair.lo); 00745 } else { 00746 tmp_res = fp_mul(fp_reg_read_lo(f3), fp_reg_read_lo(f4)); 00747 if (f2 != 0) 00748 tmp_res = fp_add(tmp_res, fp_reg_read_lo(f2), tmp_fp_env); 00749 tmp_res_lo = fp_ieee_round_sp(tmp_res, low, &tmp_fp_env); 00750 } 00751 00752 FR[f1].significand = fp_concatenate(tmp_res_hi, tmp_res_lo); 00753 FR[f1].exponent = FP_INTEGER_EXP; 00754 FR[f1].sign = FP_SIGN_POSITIVE; 00755 00756 fp_update_fpsr(sf, tmp_fp_env); 00757 fp_update_psr(f1); 00758 if (fp_raise_traps(tmp_fp_env)) 00759 fp_exception_trap(fp_decode_trap(tmp_fp_env)); 00760 } 00761 } 00762 /* EAS END */ 00763 } 00764 00765 00766 // ****************************************************************** 00767 // _fms 00768 // ****************************************************************** 00769 static INLINE void 00770 _fms(EM_state_type *ps, 00771 EM_opcode_pc_type pc, 00772 EM_opcode_sf_type sf, 00773 EM_uint_t qp, 00774 EM_uint_t f1, 00775 EM_uint_t f3, 00776 EM_uint_t f4, 00777 EM_uint_t f2) 00778 { 00779 EM_uint_t tmp_isrcode; 00780 EM_fp_reg_type tmp_fr2, tmp_default_result; 00781 EM_fp_dp_type tmp_res; 00782 EM_tmp_fp_env_type tmp_fp_env; 00783 00784 /* EAS START */ 00785 if (PR[qp]) { 00786 fp_check_target_register(f1); 00787 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, f4)) 00788 disabled_fp_register_fault(tmp_isrcode,0); 00789 00790 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3]) || fp_is_natval(FR[f4])) { 00791 FR[f1] = NATVAL; 00792 fp_update_psr(f1); 00793 } else { 00794 tmp_default_result = fms_fnma_exception_fault_check(f2, f3, f4, 00795 pc, sf, &tmp_fp_env); 00796 00797 if (fp_raise_fault(tmp_fp_env)) { 00798 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 00799 return; // MACH 00800 } 00801 00802 if (fp_is_nan_or_inf(tmp_default_result)) { 00803 FR[f1] = tmp_default_result; 00804 } else { 00805 tmp_res = fp_mul(fp_reg_read(FR[f3]), fp_reg_read(FR[f4])); 00806 tmp_fr2 = fp_reg_read(FR[f2]); 00807 tmp_fr2.sign = !tmp_fr2.sign; 00808 if (f2 != 0) 00809 tmp_res = fp_add(tmp_res, tmp_fr2, tmp_fp_env); 00810 FR[f1] = fp_ieee_round(tmp_res, &tmp_fp_env); 00811 } 00812 00813 fp_update_fpsr(sf, tmp_fp_env); 00814 fp_update_psr(f1); 00815 if (fp_raise_traps(tmp_fp_env)) 00816 fp_exception_trap(fp_decode_trap(tmp_fp_env)); 00817 } 00818 } 00819 /* EAS END */ 00820 } 00821 00822 00823 // ****************************************************************** 00824 // _fpms 00825 // ****************************************************************** 00826 static INLINE void 00827 _fpms(EM_state_type *ps, 00828 EM_opcode_sf_type sf, 00829 EM_uint_t qp, 00830 EM_uint_t f1, 00831 EM_uint_t f3, 00832 EM_uint_t f4, 00833 EM_uint_t f2) 00834 { 00835 EM_uint_t tmp_isrcode, tmp_res_hi, tmp_res_lo; 00836 EM_pair_fp_reg_type tmp_default_result_pair; 00837 EM_fp_reg_type tmp_sub; 00838 EM_fp_dp_type tmp_res; 00839 EM_tmp_fp_env_type tmp_fp_env; 00840 00841 /* EAS START */ 00842 if (PR[qp]) { 00843 fp_check_target_register(f1); 00844 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, f4)) 00845 disabled_fp_register_fault(tmp_isrcode,0); 00846 00847 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3]) || fp_is_natval(FR[f4])) { 00848 FR[f1] = NATVAL; 00849 fp_update_psr(f1); 00850 } else { 00851 tmp_default_result_pair = fpms_fpnma_exception_fault_check(f2, f3, f4, 00852 sf, &tmp_fp_env); 00853 if (fp_raise_fault(tmp_fp_env)) { 00854 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 00855 return; // MACH 00856 } 00857 00858 if (fp_is_nan_or_inf(tmp_default_result_pair.hi)) { 00859 tmp_res_hi = fp_single(tmp_default_result_pair.hi); 00860 } else { 00861 tmp_res = fp_mul(fp_reg_read_hi(f3), fp_reg_read_hi(f4)); 00862 if (f2 != 0) { 00863 tmp_sub = fp_reg_read_hi(f2); 00864 tmp_sub.sign = !tmp_sub.sign; 00865 tmp_res = fp_add(tmp_res, tmp_sub, tmp_fp_env); 00866 } 00867 tmp_res_hi = fp_ieee_round_sp(tmp_res, high, &tmp_fp_env); 00868 } 00869 00870 if (fp_is_nan_or_inf(tmp_default_result_pair.lo)) { 00871 tmp_res_lo = fp_single(tmp_default_result_pair.lo); 00872 } else { 00873 tmp_res = fp_mul(fp_reg_read_lo(f3), fp_reg_read_lo(f4)); 00874 if (f2 != 0) { 00875 tmp_sub = fp_reg_read_lo(f2); 00876 tmp_sub.sign = !tmp_sub.sign; 00877 tmp_res = fp_add(tmp_res, tmp_sub, tmp_fp_env); 00878 } 00879 tmp_res_lo = fp_ieee_round_sp(tmp_res, low, &tmp_fp_env); 00880 } 00881 00882 FR[f1].significand = fp_concatenate(tmp_res_hi, tmp_res_lo); 00883 FR[f1].exponent = FP_INTEGER_EXP; 00884 FR[f1].sign = FP_SIGN_POSITIVE; 00885 00886 fp_update_fpsr(sf, tmp_fp_env); 00887 fp_update_psr(f1); 00888 if (fp_raise_traps(tmp_fp_env)) 00889 fp_exception_trap(fp_decode_trap(tmp_fp_env)); 00890 } 00891 } 00892 /* EAS END */ 00893 } 00894 00895 00896 // ****************************************************************** 00897 // _fnma 00898 // ****************************************************************** 00899 static INLINE void 00900 _fnma(EM_state_type *ps, 00901 EM_opcode_pc_type pc, 00902 EM_opcode_sf_type sf, 00903 EM_uint_t qp, 00904 EM_uint_t f1, 00905 EM_uint_t f3, 00906 EM_uint_t f4, 00907 EM_uint_t f2) 00908 { 00909 EM_uint_t tmp_isrcode; 00910 EM_fp_reg_type tmp_default_result; 00911 EM_tmp_fp_env_type tmp_fp_env; 00912 EM_fp_dp_type tmp_res; 00913 00914 /* EAS START */ 00915 if (PR[qp]) { 00916 fp_check_target_register(f1); 00917 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, f4)) 00918 disabled_fp_register_fault(tmp_isrcode,0); 00919 00920 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3]) || fp_is_natval(FR[f4])) { 00921 FR[f1] = NATVAL; 00922 fp_update_psr(f1); 00923 } else { 00924 tmp_default_result = fms_fnma_exception_fault_check(f2, f3, f4, 00925 pc, sf, &tmp_fp_env); 00926 00927 if (fp_raise_fault(tmp_fp_env)) { 00928 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 00929 return; // MACH 00930 } 00931 00932 if (fp_is_nan_or_inf(tmp_default_result)) { 00933 FR[f1] = tmp_default_result; 00934 } else { 00935 tmp_res = fp_mul(fp_reg_read(FR[f3]), fp_reg_read(FR[f4])); 00936 tmp_res.sign = !tmp_res.sign; 00937 if (f2 != 0) 00938 tmp_res = fp_add(tmp_res, fp_reg_read(FR[f2]), tmp_fp_env); 00939 FR[f1] = fp_ieee_round(tmp_res, &tmp_fp_env); 00940 } 00941 00942 fp_update_fpsr(sf, tmp_fp_env); 00943 fp_update_psr(f1); 00944 if (fp_raise_traps(tmp_fp_env)) 00945 fp_exception_trap(fp_decode_trap(tmp_fp_env)); 00946 } 00947 } 00948 /* EAS END */ 00949 } 00950 00951 // ****************************************************************** 00952 // _fpnma 00953 // ****************************************************************** 00954 static INLINE void 00955 _fpnma(EM_state_type *ps, 00956 EM_opcode_sf_type sf, 00957 EM_uint_t qp, 00958 EM_uint_t f1, 00959 EM_uint_t f3, 00960 EM_uint_t f4, 00961 EM_uint_t f2) 00962 { 00963 EM_uint_t tmp_isrcode, tmp_res_hi, tmp_res_lo; 00964 EM_pair_fp_reg_type tmp_default_result_pair; 00965 EM_tmp_fp_env_type tmp_fp_env; 00966 EM_fp_dp_type tmp_res; 00967 00968 /* EAS START */ 00969 if (PR[qp]) { 00970 fp_check_target_register(f1); 00971 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, f4)) 00972 disabled_fp_register_fault(tmp_isrcode,0); 00973 00974 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3]) || fp_is_natval(FR[f4])) { 00975 FR[f1] = NATVAL; 00976 fp_update_psr(f1); 00977 } else { 00978 tmp_default_result_pair = fpms_fpnma_exception_fault_check(f2, f3, f4, 00979 sf, &tmp_fp_env); 00980 if (fp_raise_fault(tmp_fp_env)) { 00981 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 00982 return; // MACH 00983 } 00984 00985 if (fp_is_nan_or_inf(tmp_default_result_pair.hi)) { 00986 tmp_res_hi = fp_single(tmp_default_result_pair.hi); 00987 } else { 00988 tmp_res = fp_mul(fp_reg_read_hi(f3), fp_reg_read_hi(f4)); 00989 tmp_res.sign = !tmp_res.sign; 00990 if (f2 != 0) 00991 tmp_res = fp_add(tmp_res, fp_reg_read_hi(f2), tmp_fp_env); 00992 tmp_res_hi = fp_ieee_round_sp(tmp_res, high, &tmp_fp_env); 00993 } 00994 00995 if (fp_is_nan_or_inf(tmp_default_result_pair.lo)) { 00996 tmp_res_lo = fp_single(tmp_default_result_pair.lo); 00997 } else { 00998 tmp_res = fp_mul(fp_reg_read_lo(f3), fp_reg_read_lo(f4)); 00999 tmp_res.sign = !tmp_res.sign; 01000 if (f2 != 0) 01001 tmp_res = fp_add(tmp_res, fp_reg_read_lo(f2), tmp_fp_env); 01002 tmp_res_lo = fp_ieee_round_sp(tmp_res, low, &tmp_fp_env); 01003 } 01004 01005 FR[f1].significand = fp_concatenate(tmp_res_hi, tmp_res_lo); 01006 FR[f1].exponent = FP_INTEGER_EXP; 01007 FR[f1].sign = FP_SIGN_POSITIVE; 01008 01009 fp_update_fpsr(sf, tmp_fp_env); 01010 fp_update_psr(f1); 01011 if (fp_raise_traps(tmp_fp_env)) 01012 fp_exception_trap(fp_decode_trap(tmp_fp_env)); 01013 } 01014 } 01015 /* EAS END */ 01016 } 01017 01018 01019 // ****************************************************************** 01020 // _fcmp 01021 // ****************************************************************** 01022 static INLINE void 01023 _fcmp(EM_state_type *ps, 01024 EM_opcode_frel_type frel, 01025 EM_opcode_ctype_type fctype, 01026 EM_opcode_sf_type sf, 01027 EM_uint_t qp, 01028 EM_uint_t p1, 01029 EM_uint_t p2, 01030 EM_uint_t f2, 01031 EM_uint_t f3) 01032 { 01033 EM_uint_t tmp_isrcode; 01034 EM_fp_reg_type tmp_fr2, tmp_fr3; 01035 EM_tmp_fp_env_type tmp_fp_env; 01036 EM_boolean_t tmp_rel; 01037 01038 /* EAS START */ 01039 if (PR[qp]) { 01040 if(p1==p2) 01041 illegal_operation_fault(0); 01042 if (tmp_isrcode = fp_reg_disabled(f2, f3, 0, 0)) 01043 disabled_fp_register_fault(tmp_isrcode,0); 01044 01045 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3])) { 01046 PR[p1] = 0; 01047 PR[p2] = 0; 01048 } else { 01049 fcmp_exception_fault_check(f2, f3, frel, sf, &tmp_fp_env); 01050 if (fp_raise_fault(tmp_fp_env)) { 01051 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01052 return; // MACH 01053 } 01054 01055 tmp_fr2 = fp_reg_read(FR[f2]); 01056 tmp_fr3 = fp_reg_read(FR[f3]); 01057 01058 if (frel == frelEQ) tmp_rel = fp_equal(tmp_fr2, tmp_fr3); 01059 else if (frel == frelLT) tmp_rel = fp_less_than(tmp_fr2, tmp_fr3); 01060 else if (frel == frelLE) tmp_rel = fp_lesser_or_equal(tmp_fr2, tmp_fr3); 01061 else if (frel == frelGT) tmp_rel = fp_less_than(tmp_fr3, tmp_fr2); 01062 else if (frel == frelGE) tmp_rel = fp_lesser_or_equal(tmp_fr3, tmp_fr2); 01063 else if (frel == frelUNORD) tmp_rel = fp_unordered(tmp_fr2, tmp_fr3); 01064 else if (frel == frelNEQ) tmp_rel = !fp_equal(tmp_fr2, tmp_fr3); 01065 else if (frel == frelNLT) tmp_rel = !fp_less_than(tmp_fr2, tmp_fr3); 01066 else if (frel == frelNLE) tmp_rel = !fp_lesser_or_equal(tmp_fr2, tmp_fr3); 01067 else if (frel == frelNGT) tmp_rel = !fp_less_than(tmp_fr3, tmp_fr2); 01068 else if (frel == frelNGE) tmp_rel = !fp_lesser_or_equal(tmp_fr3, tmp_fr2); 01069 else tmp_rel = !fp_unordered(tmp_fr2, tmp_fr3); 01070 01071 PR[p1] = tmp_rel; 01072 PR[p2] = !tmp_rel; 01073 fp_update_fpsr(sf, tmp_fp_env); 01074 } 01075 01076 } else { 01077 if (fctype == fctypeUNC) { 01078 if(p1==p2) 01079 illegal_operation_fault(0); 01080 PR[p1] = 0; 01081 PR[p2] = 0; 01082 } 01083 } 01084 /* EAS END */ 01085 } 01086 01087 // ****************************************************************** 01088 // _frcpa 01089 // ****************************************************************** 01090 static INLINE void 01091 _frcpa(EM_state_type *ps, 01092 EM_opcode_sf_type sf, 01093 EM_uint_t qp, 01094 EM_uint_t f1, 01095 EM_uint_t p2, 01096 EM_uint_t f2, 01097 EM_uint_t f3) 01098 { 01099 EM_uint_t tmp_isrcode; 01100 EM_fp_reg_type tmp_default_result, num, den; 01101 EM_tmp_fp_env_type tmp_fp_env; 01102 01103 /* EAS START */ 01104 if (PR[qp]) { 01105 fp_check_target_register(f1); 01106 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, 0)) 01107 disabled_fp_register_fault(tmp_isrcode,0); 01108 01109 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3])) { 01110 FR[f1] = NATVAL; 01111 PR[p2] = 0; 01112 } else { 01113 tmp_default_result = frcpa_exception_fault_check(f2, f3, sf, &tmp_fp_env); 01114 if (fp_raise_fault(tmp_fp_env)) { 01115 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01116 return; // MACH 01117 } 01118 01119 if (fp_is_nan_or_inf(tmp_default_result)) { 01120 FR[f1] = tmp_default_result; 01121 PR[p2] = 0; 01122 01123 } else { 01124 num = fp_normalize(fp_reg_read(FR[f2])); 01125 den = fp_normalize(fp_reg_read(FR[f3])); 01126 if (fp_is_inf(num) && fp_is_finite(den)) { 01127 FR[f1] = FP_INFINITY; 01128 FR[f1].sign = num.sign ^ den.sign; 01129 PR[p2] = 0; 01130 01131 } else if (fp_is_finite(num) && fp_is_inf(den)) { 01132 FR[f1] = FP_ZERO; 01133 FR[f1].sign = num.sign ^ den.sign; 01134 PR[p2] = 0; 01135 01136 } else if (fp_is_zero(num) && fp_is_finite(den)) { 01137 FR[f1] = FP_ZERO; 01138 FR[f1].sign = num.sign ^ den.sign; 01139 PR[p2] = 0; 01140 01141 } else { 01142 FR[f1] = fp_ieee_recip(den); 01143 PR[p2] = 1; 01144 } 01145 } 01146 fp_update_fpsr(sf, tmp_fp_env); 01147 } 01148 fp_update_psr(f1); 01149 } else { 01150 PR[p2] = 0; 01151 } 01152 /* EAS END */ 01153 } 01154 01155 // ****************************************************************** 01156 // _fprcpa 01157 // ****************************************************************** 01158 static INLINE void 01159 _fprcpa(EM_state_type *ps, 01160 EM_opcode_sf_type sf, 01161 EM_uint_t qp, 01162 EM_uint_t f1, 01163 EM_uint_t p2, 01164 EM_uint_t f2, 01165 EM_uint_t f3) 01166 { 01167 EM_uint_t tmp_isrcode, tmp_res_hi, tmp_res_lo; 01168 EM_pair_fp_reg_type tmp_default_result_pair; 01169 EM_fp_reg_type tmp_res, num, den; 01170 EM_boolean_t tmp_pred_hi, tmp_pred_lo; 01171 EM_tmp_fp_env_type tmp_fp_env; 01172 EM_limits_check_fprcpa limits_check = {0,0,0,0}; 01173 01174 /* EAS START */ 01175 if (PR[qp]) { 01176 fp_check_target_register(f1); 01177 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, 0)) 01178 disabled_fp_register_fault(tmp_isrcode,0); 01179 01180 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3])) { 01181 FR[f1] = NATVAL; 01182 PR[p2] = 0; 01183 } else { 01184 tmp_default_result_pair = fprcpa_exception_fault_check(f2, f3, sf, 01185 &tmp_fp_env, &limits_check); 01186 if (fp_raise_fault(tmp_fp_env)) { 01187 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01188 return; // MACH 01189 } 01190 01191 if (fp_is_nan_or_inf(tmp_default_result_pair.hi) || limits_check.hi_fr3) { 01192 tmp_res_hi = fp_single(tmp_default_result_pair.hi); 01193 tmp_pred_hi = 0; 01194 01195 } else { 01196 num = fp_normalize(fp_reg_read_hi(f2)); 01197 den = fp_normalize(fp_reg_read_hi(f3)); 01198 01199 if (fp_is_inf(num) && fp_is_finite(den)) { 01200 tmp_res = FP_INFINITY; 01201 tmp_res.sign = num.sign ^ den.sign; 01202 tmp_pred_hi = 0; 01203 01204 } else if (fp_is_finite(num) && fp_is_inf(den)) { 01205 tmp_res = FP_ZERO; 01206 tmp_res.sign = num.sign ^ den.sign; 01207 tmp_pred_hi = 0; 01208 01209 } else if (fp_is_zero(num) && fp_is_finite(den)) { 01210 tmp_res = FP_ZERO; 01211 tmp_res.sign = num.sign ^ den.sign; 01212 tmp_pred_hi = 0; 01213 01214 } else { 01215 tmp_res = fp_ieee_recip(den); 01216 if (limits_check.hi_fr2_or_quot) { 01217 tmp_pred_hi = 0; 01218 } else { 01219 tmp_pred_hi = 1; 01220 } 01221 } 01222 tmp_res_hi = fp_single(tmp_res); 01223 } 01224 01225 01226 if (fp_is_nan_or_inf(tmp_default_result_pair.lo) || limits_check.lo_fr3) { 01227 tmp_res_lo = fp_single(tmp_default_result_pair.lo); 01228 tmp_pred_lo = 0; 01229 } else { 01230 num = fp_normalize(fp_reg_read_lo(f2)); 01231 den = fp_normalize(fp_reg_read_lo(f3)); 01232 01233 if (fp_is_inf(num) && fp_is_finite(den)) { 01234 tmp_res = FP_INFINITY; 01235 tmp_res.sign = num.sign ^ den.sign; 01236 tmp_pred_lo = 0; 01237 01238 } else if (fp_is_finite(num) && fp_is_inf(den)) { 01239 tmp_res = FP_ZERO; 01240 tmp_res.sign = num.sign ^ den.sign; 01241 tmp_pred_lo = 0; 01242 01243 } else if (fp_is_zero(num) && fp_is_finite(den)) { 01244 tmp_res = FP_ZERO; 01245 tmp_res.sign = num.sign ^ den.sign; 01246 tmp_pred_lo = 0; 01247 01248 } else { 01249 tmp_res = fp_ieee_recip(den); 01250 if (limits_check.lo_fr2_or_quot) { 01251 tmp_pred_lo = 0; 01252 } else { 01253 tmp_pred_lo = 1; 01254 } 01255 } 01256 tmp_res_lo = fp_single(tmp_res); 01257 } 01258 01259 FR[f1].significand = fp_concatenate(tmp_res_hi, tmp_res_lo); 01260 FR[f1].exponent = FP_INTEGER_EXP; 01261 FR[f1].sign = FP_SIGN_POSITIVE; 01262 PR[p2] = tmp_pred_hi && tmp_pred_lo; 01263 01264 fp_update_fpsr(sf, tmp_fp_env); 01265 } 01266 fp_update_psr(f1); 01267 } else { 01268 PR[p2] = 0; /* unconditional semantics */ 01269 } 01270 /* EAS END */ 01271 } 01272 01273 // ****************************************************************** 01274 // _frsqrta 01275 // ****************************************************************** 01276 static INLINE void 01277 _frsqrta(EM_state_type *ps, 01278 EM_opcode_sf_type sf, 01279 EM_uint_t qp, 01280 EM_uint_t f1, 01281 EM_uint_t p2, 01282 EM_uint_t f3) 01283 { 01284 EM_uint_t tmp_isrcode; 01285 EM_fp_reg_type tmp_default_result, tmp_fr3; 01286 EM_tmp_fp_env_type tmp_fp_env; 01287 01288 /* EAS START */ 01289 if (PR[qp]) { 01290 fp_check_target_register(f1); 01291 if (tmp_isrcode = fp_reg_disabled(f1, f3, 0, 0)) 01292 disabled_fp_register_fault(tmp_isrcode,0); 01293 01294 if (fp_is_natval(FR[f3])) { 01295 FR[f1] = NATVAL; 01296 PR[p2] = 0; 01297 } else { 01298 tmp_default_result = frsqrta_exception_fault_check(f3, sf, &tmp_fp_env); 01299 if (fp_raise_fault(tmp_fp_env)) { 01300 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01301 return; // MACH 01302 } 01303 01304 if (fp_is_nan_or_inf(tmp_default_result)) { 01305 FR[f1] = tmp_default_result; 01306 PR[p2] = 0; 01307 } else { 01308 tmp_fr3 = fp_normalize(fp_reg_read(FR[f3])); 01309 if (fp_is_zero(tmp_fr3)) { 01310 FR[f1] = tmp_fr3; 01311 PR[p2] = 0; 01312 } else if (fp_is_pos_inf(tmp_fr3)) { 01313 FR[f1] = tmp_fr3; 01314 PR[p2] = 0; 01315 } else { 01316 FR[f1] = fp_ieee_recip_sqrt(tmp_fr3); 01317 PR[p2] = 1; 01318 } 01319 } 01320 fp_update_fpsr(sf, tmp_fp_env); 01321 } 01322 fp_update_psr(f1); 01323 } else { 01324 PR[p2] = 0; 01325 } 01326 /* EAS END */ 01327 } 01328 01329 // ****************************************************************** 01330 // _fprsqrta 01331 // ****************************************************************** 01332 static INLINE void 01333 _fprsqrta(EM_state_type *ps, 01334 EM_opcode_sf_type sf, 01335 EM_uint_t qp, 01336 EM_uint_t f1, 01337 EM_uint_t p2, 01338 EM_uint_t f3) 01339 { 01340 EM_uint_t tmp_isrcode, tmp_res_hi, tmp_res_lo; 01341 EM_pair_fp_reg_type tmp_default_result_pair; 01342 EM_fp_reg_type tmp_res, tmp_fr3; 01343 EM_boolean_t tmp_pred_hi, tmp_pred_lo; 01344 EM_tmp_fp_env_type tmp_fp_env; 01345 EM_limits_check_fprsqrta limits_check = {0, 0}; 01346 01347 /* EAS START */ 01348 if (PR[qp]) { 01349 fp_check_target_register(f1); 01350 if (tmp_isrcode = fp_reg_disabled(f1, f3, 0, 0)) 01351 disabled_fp_register_fault(tmp_isrcode,0); 01352 01353 if( fp_is_natval(FR[f3])) { 01354 PR[p2] = 0; 01355 FR[f1] = NATVAL; 01356 } else { 01357 tmp_default_result_pair = fprsqrta_exception_fault_check(f3, sf, 01358 &tmp_fp_env, &limits_check); 01359 if(fp_raise_fault(tmp_fp_env)) { 01360 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01361 return; // MACH 01362 } 01363 01364 if (fp_is_nan(tmp_default_result_pair.hi) ) { 01365 tmp_res_hi = fp_single(tmp_default_result_pair.hi); 01366 tmp_pred_hi = 0; 01367 } else { 01368 tmp_fr3 = fp_normalize(fp_reg_read_hi(f3)); 01369 if (fp_is_zero(tmp_fr3)) { 01370 tmp_res = FP_INFINITY; 01371 tmp_res.sign = tmp_fr3.sign; 01372 tmp_pred_hi = 0; 01373 } else if (fp_is_pos_inf(tmp_fr3)) { 01374 tmp_res = FP_ZERO; 01375 tmp_pred_hi = 0; 01376 } else { 01377 tmp_res = fp_ieee_recip_sqrt(tmp_fr3); 01378 if (limits_check.hi) 01379 tmp_pred_hi = 0; 01380 else 01381 tmp_pred_hi = 1; 01382 } 01383 tmp_res_hi = fp_single(tmp_res); 01384 } 01385 01386 01387 if (fp_is_nan(tmp_default_result_pair.lo) ) { 01388 tmp_res_lo = fp_single(tmp_default_result_pair.lo); 01389 tmp_pred_lo = 0; 01390 } else { 01391 tmp_fr3 = fp_normalize(fp_reg_read_lo(f3)); 01392 if (fp_is_zero(tmp_fr3)) { 01393 tmp_res = FP_INFINITY; 01394 tmp_res.sign = tmp_fr3.sign; 01395 tmp_pred_lo = 0; 01396 } else if (fp_is_pos_inf(tmp_fr3)) { 01397 tmp_res = FP_ZERO; 01398 tmp_pred_lo = 0; 01399 } else { 01400 tmp_res = fp_ieee_recip_sqrt(tmp_fr3); 01401 if (limits_check.lo) 01402 tmp_pred_lo = 0; 01403 else 01404 tmp_pred_lo = 1; 01405 } 01406 tmp_res_lo = fp_single(tmp_res); 01407 } 01408 01409 FR[f1].significand = fp_concatenate(tmp_res_hi,tmp_res_lo); 01410 FR[f1].exponent = FP_INTEGER_EXP; 01411 FR[f1].sign = FP_SIGN_POSITIVE; 01412 PR[p2] = tmp_pred_hi & tmp_pred_lo; 01413 01414 fp_update_fpsr(sf, tmp_fp_env); 01415 } 01416 fp_update_psr(f1); 01417 } else { 01418 PR[p2] = 0; 01419 } 01420 /* EAS END */ 01421 } 01422 01423 01424 // ****************************************************************** 01425 // _fmin 01426 // ****************************************************************** 01427 static INLINE void 01428 _fmin(EM_state_type *ps, 01429 EM_opcode_sf_type sf, 01430 EM_uint_t qp, 01431 EM_uint_t f1, 01432 EM_uint_t f2, 01433 EM_uint_t f3) 01434 { 01435 EM_uint_t tmp_isrcode; 01436 EM_tmp_fp_env_type tmp_fp_env; 01437 EM_boolean_t tmp_bool_res; 01438 01439 /* EAS START */ 01440 if (PR[qp]) { 01441 fp_check_target_register(f1); 01442 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, 0)) 01443 disabled_fp_register_fault(tmp_isrcode,0); 01444 01445 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3])) { 01446 FR[f1] = NATVAL; 01447 } else { 01448 fminmax_exception_fault_check(f2, f3, sf, &tmp_fp_env); 01449 01450 if (fp_raise_fault(tmp_fp_env)) { 01451 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01452 return; // MACH 01453 } 01454 01455 tmp_bool_res = fp_less_than(fp_reg_read(FR[f2]), fp_reg_read(FR[f3])); 01456 FR[f1] = tmp_bool_res ? FR[f2] : FR[f3]; 01457 01458 fp_update_fpsr(sf, tmp_fp_env); 01459 } 01460 fp_update_psr(f1); 01461 } 01462 /* EAS END */ 01463 } 01464 01465 01466 // ****************************************************************** 01467 // _fmax 01468 // ****************************************************************** 01469 static INLINE void 01470 _fmax(EM_state_type *ps, 01471 EM_opcode_sf_type sf, 01472 EM_uint_t qp, 01473 EM_uint_t f1, 01474 EM_uint_t f2, 01475 EM_uint_t f3) 01476 { 01477 EM_uint_t tmp_isrcode; 01478 EM_tmp_fp_env_type tmp_fp_env; 01479 EM_boolean_t tmp_bool_res; 01480 01481 /* EAS START */ 01482 if (PR[qp]) { 01483 fp_check_target_register(f1); 01484 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, 0)) 01485 disabled_fp_register_fault(tmp_isrcode,0); 01486 01487 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3])) { 01488 FR[f1] = NATVAL; 01489 } else { 01490 fminmax_exception_fault_check(f2, f3, sf, &tmp_fp_env); 01491 if (fp_raise_fault(tmp_fp_env)) { 01492 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01493 return; // MACH 01494 } 01495 01496 tmp_bool_res = fp_less_than(fp_reg_read(FR[f3]), fp_reg_read(FR[f2])); 01497 FR[f1] = (tmp_bool_res ? FR[f2] : FR[f3]); 01498 01499 fp_update_fpsr(sf, tmp_fp_env); 01500 } 01501 fp_update_psr(f1); 01502 } 01503 /* EAS END */ 01504 } 01505 01506 01507 // ****************************************************************** 01508 // _famin 01509 // ****************************************************************** 01510 static INLINE void 01511 _famin(EM_state_type *ps, 01512 EM_opcode_sf_type sf, 01513 EM_uint_t qp, 01514 EM_uint_t f1, 01515 EM_uint_t f2, 01516 EM_uint_t f3) 01517 { 01518 EM_uint_t tmp_isrcode; 01519 EM_fp_reg_type tmp_right, tmp_left; 01520 EM_tmp_fp_env_type tmp_fp_env; 01521 EM_boolean_t tmp_bool_res; 01522 01523 01524 /* EAS START */ 01525 if (PR[qp]) { 01526 fp_check_target_register(f1); 01527 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, 0)) 01528 disabled_fp_register_fault(tmp_isrcode,0); 01529 01530 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3])) { 01531 FR[f1] = NATVAL; 01532 } else { 01533 fminmax_exception_fault_check(f2, f3, sf, &tmp_fp_env); 01534 if (fp_raise_fault(tmp_fp_env)) { 01535 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01536 return; // MACH 01537 } 01538 01539 tmp_left = fp_reg_read(FR[f2]); 01540 tmp_right = fp_reg_read(FR[f3]); 01541 tmp_left.sign = FP_SIGN_POSITIVE; 01542 tmp_right.sign = FP_SIGN_POSITIVE; 01543 tmp_bool_res = fp_less_than(tmp_left, tmp_right); 01544 FR[f1] = tmp_bool_res ? FR[f2] : FR[f3]; 01545 01546 fp_update_fpsr(sf, tmp_fp_env); 01547 } 01548 fp_update_psr(f1); 01549 } 01550 /* EAS END */ 01551 } 01552 01553 01554 // ****************************************************************** 01555 // _famax 01556 // ****************************************************************** 01557 static INLINE void 01558 _famax(EM_state_type *ps, 01559 EM_opcode_sf_type sf, 01560 EM_uint_t qp, 01561 EM_uint_t f1, 01562 EM_uint_t f2, 01563 EM_uint_t f3) 01564 { 01565 EM_uint_t tmp_isrcode; 01566 EM_fp_reg_type tmp_right, tmp_left; 01567 EM_tmp_fp_env_type tmp_fp_env; 01568 EM_boolean_t tmp_bool_res; 01569 01570 01571 /* EAS START */ 01572 if (PR[qp]) { 01573 fp_check_target_register(f1); 01574 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, 0) ) 01575 disabled_fp_register_fault(tmp_isrcode,0); 01576 01577 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3])) { 01578 FR[f1] = NATVAL; 01579 } else { 01580 fminmax_exception_fault_check(f2, f3, sf, &tmp_fp_env); 01581 01582 if (fp_raise_fault(tmp_fp_env)) { 01583 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01584 return; // MACH 01585 } 01586 01587 tmp_right = fp_reg_read(FR[f2]); 01588 tmp_left = fp_reg_read(FR[f3]); 01589 tmp_right.sign = FP_SIGN_POSITIVE; 01590 tmp_left.sign = FP_SIGN_POSITIVE; 01591 tmp_bool_res = fp_less_than(tmp_left, tmp_right); 01592 01593 FR[f1] = tmp_bool_res ? FR[f2] : FR[f3]; 01594 fp_update_fpsr(sf, tmp_fp_env); 01595 } 01596 fp_update_psr(f1); 01597 } 01598 /* EAS END */ 01599 } 01600 01601 // ****************************************************************** 01602 // _fpmin 01603 // ****************************************************************** 01604 static INLINE void 01605 _fpmin(EM_state_type *ps, 01606 EM_opcode_sf_type sf, 01607 EM_uint_t qp, 01608 EM_uint_t f1, 01609 EM_uint_t f2, 01610 EM_uint_t f3) 01611 { 01612 EM_uint_t tmp_isrcode, tmp_res_hi, tmp_res_lo; 01613 EM_fp_reg_type tmp_right, tmp_left, tmp_fr2, tmp_fr3; 01614 EM_tmp_fp_env_type tmp_fp_env; 01615 EM_boolean_t tmp_bool_res; 01616 01617 /* EAS START */ 01618 if (PR[qp]) { 01619 fp_check_target_register(f1); 01620 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, 0)) 01621 disabled_fp_register_fault(tmp_isrcode,0); 01622 01623 if (fp_is_natval(FR[f2] ) || fp_is_natval(FR[f3]) ) { 01624 FR[f1] = NATVAL; 01625 } else { 01626 fpminmax_exception_fault_check(f2, f3, sf, &tmp_fp_env); 01627 if (fp_raise_fault(tmp_fp_env)) { 01628 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01629 return; // MACH 01630 } 01631 01632 tmp_fr2 = tmp_left = fp_reg_read_hi(f2); 01633 tmp_fr3 = tmp_right = fp_reg_read_hi(f3); 01634 tmp_bool_res = fp_less_than(tmp_left, tmp_right); 01635 tmp_res_hi = fp_single(tmp_bool_res ? tmp_fr2: tmp_fr3); 01636 01637 tmp_fr2 = tmp_left = fp_reg_read_lo(f2); 01638 tmp_fr3 = tmp_right = fp_reg_read_lo(f3); 01639 tmp_bool_res = fp_less_than(tmp_left, tmp_right); 01640 tmp_res_lo = fp_single(tmp_bool_res ? tmp_fr2: tmp_fr3); 01641 01642 FR[f1].significand = fp_concatenate(tmp_res_hi, tmp_res_lo); 01643 FR[f1].exponent = FP_INTEGER_EXP; 01644 FR[f1].sign = FP_SIGN_POSITIVE; 01645 01646 fp_update_fpsr(sf, tmp_fp_env); 01647 } 01648 fp_update_psr(f1); 01649 } 01650 /* EAS END */ 01651 } 01652 01653 // ****************************************************************** 01654 // _fpmax 01655 // ****************************************************************** 01656 static INLINE void 01657 _fpmax(EM_state_type *ps, 01658 EM_opcode_sf_type sf, 01659 EM_uint_t qp, 01660 EM_uint_t f1, 01661 EM_uint_t f2, 01662 EM_uint_t f3) 01663 { 01664 EM_uint_t tmp_isrcode, tmp_res_hi, tmp_res_lo; 01665 EM_fp_reg_type tmp_right, tmp_left, tmp_fr2, tmp_fr3; 01666 EM_tmp_fp_env_type tmp_fp_env; 01667 EM_boolean_t tmp_bool_res; 01668 01669 /* EAS START */ 01670 if (PR[qp]) { 01671 fp_check_target_register(f1); 01672 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, 0)) 01673 disabled_fp_register_fault(tmp_isrcode,0); 01674 01675 if (fp_is_natval(FR[f2] ) || fp_is_natval(FR[f3]) ) { 01676 FR[f1] = NATVAL; 01677 } else { 01678 fpminmax_exception_fault_check(f2, f3, sf, &tmp_fp_env); 01679 if (fp_raise_fault(tmp_fp_env)) { 01680 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01681 return; // MACH 01682 } 01683 01684 tmp_fr2 = tmp_right = fp_reg_read_hi(f2); 01685 tmp_fr3 = tmp_left = fp_reg_read_hi(f3); 01686 tmp_bool_res = fp_less_than(tmp_left, tmp_right); 01687 tmp_res_hi = fp_single(tmp_bool_res ? tmp_fr2 : tmp_fr3); 01688 01689 tmp_fr2 = tmp_right = fp_reg_read_lo(f2); 01690 tmp_fr3 = tmp_left = fp_reg_read_lo(f3); 01691 tmp_bool_res = fp_less_than(tmp_left, tmp_right); 01692 tmp_res_lo = fp_single(tmp_bool_res ? tmp_fr2: tmp_fr3); 01693 01694 FR[f1].significand = fp_concatenate(tmp_res_hi, tmp_res_lo); 01695 FR[f1].exponent = FP_INTEGER_EXP; 01696 FR[f1].sign = FP_SIGN_POSITIVE; 01697 fp_update_fpsr(sf, tmp_fp_env); 01698 } 01699 fp_update_psr(f1); 01700 } 01701 /* EAS END */ 01702 } 01703 01704 // ****************************************************************** 01705 // _fpamin 01706 // ****************************************************************** 01707 static INLINE void 01708 _fpamin(EM_state_type *ps, 01709 EM_opcode_sf_type sf, 01710 EM_uint_t qp, 01711 EM_uint_t f1, 01712 EM_uint_t f2, 01713 EM_uint_t f3) 01714 { 01715 EM_uint_t tmp_isrcode, tmp_res_hi, tmp_res_lo; 01716 EM_fp_reg_type tmp_right, tmp_left, tmp_fr2, tmp_fr3; 01717 EM_tmp_fp_env_type tmp_fp_env; 01718 EM_boolean_t tmp_bool_res; 01719 01720 /* EAS START */ 01721 if (PR[qp]) { 01722 fp_check_target_register(f1); 01723 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, 0)) 01724 disabled_fp_register_fault(tmp_isrcode,0); 01725 01726 if (fp_is_natval(FR[f2] ) || fp_is_natval(FR[f3]) ) { 01727 FR[f1] = NATVAL; 01728 } else { 01729 fpminmax_exception_fault_check(f2,f3, sf, &tmp_fp_env); 01730 if(fp_raise_fault(tmp_fp_env)) { 01731 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01732 return; // MACH 01733 } 01734 01735 01736 tmp_fr2 = tmp_left = fp_reg_read_hi(f2); 01737 tmp_fr3 = tmp_right = fp_reg_read_hi(f3); 01738 tmp_left.sign = FP_SIGN_POSITIVE; 01739 tmp_right.sign = FP_SIGN_POSITIVE; 01740 tmp_bool_res = fp_less_than(tmp_left, tmp_right); 01741 tmp_res_hi = fp_single(tmp_bool_res ? tmp_fr2 : tmp_fr3); 01742 01743 01744 tmp_fr2 = tmp_left = fp_reg_read_lo(f2); 01745 tmp_fr3 = tmp_right = fp_reg_read_lo(f3); 01746 tmp_left.sign = FP_SIGN_POSITIVE; 01747 tmp_right.sign = FP_SIGN_POSITIVE; 01748 tmp_bool_res = fp_less_than(tmp_left, tmp_right); 01749 tmp_res_lo = fp_single(tmp_bool_res ? tmp_fr2: tmp_fr3); 01750 01751 FR[f1].significand = fp_concatenate(tmp_res_hi, tmp_res_lo); 01752 FR[f1].exponent = FP_INTEGER_EXP; 01753 FR[f1].sign = FP_SIGN_POSITIVE; 01754 01755 fp_update_fpsr(sf, tmp_fp_env); 01756 } 01757 fp_update_psr(f1); 01758 } 01759 /* EAS END */ 01760 } 01761 01762 01763 // ****************************************************************** 01764 // _fpamax 01765 // ****************************************************************** 01766 static INLINE void 01767 _fpamax(EM_state_type *ps, 01768 EM_opcode_sf_type sf, 01769 EM_uint_t qp, 01770 EM_uint_t f1, 01771 EM_uint_t f2, 01772 EM_uint_t f3) 01773 { 01774 EM_uint_t tmp_isrcode, tmp_res_hi, tmp_res_lo; 01775 EM_fp_reg_type tmp_right, tmp_left, tmp_fr2, tmp_fr3; 01776 EM_tmp_fp_env_type tmp_fp_env; 01777 EM_boolean_t tmp_bool_res; 01778 01779 01780 /* EAS START */ 01781 if (PR[qp]) { 01782 fp_check_target_register(f1); 01783 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, 0)) 01784 disabled_fp_register_fault(tmp_isrcode,0); 01785 01786 if (fp_is_natval(FR[f2] ) || fp_is_natval(FR[f3]) ) { 01787 FR[f1] = NATVAL; 01788 } else { 01789 fpminmax_exception_fault_check(f2, f3, sf, &tmp_fp_env); 01790 if (fp_raise_fault(tmp_fp_env)) { 01791 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01792 return; // MACH 01793 } 01794 01795 01796 tmp_fr2 = tmp_right = fp_reg_read_hi(f2); 01797 tmp_fr3 = tmp_left = fp_reg_read_hi(f3); 01798 tmp_right.sign = FP_SIGN_POSITIVE; 01799 tmp_left.sign = FP_SIGN_POSITIVE; 01800 tmp_bool_res = fp_less_than(tmp_left, tmp_right); 01801 tmp_res_hi = fp_single(tmp_bool_res ? tmp_fr2: tmp_fr3); 01802 01803 01804 tmp_fr2 = tmp_right = fp_reg_read_lo(f2); 01805 tmp_fr3 = tmp_left = fp_reg_read_lo(f3); 01806 tmp_right.sign = FP_SIGN_POSITIVE; 01807 tmp_left.sign = FP_SIGN_POSITIVE; 01808 tmp_bool_res = fp_less_than(tmp_left, tmp_right); 01809 tmp_res_lo = fp_single(tmp_bool_res ? tmp_fr2: tmp_fr3); 01810 01811 FR[f1].significand = fp_concatenate(tmp_res_hi, tmp_res_lo); 01812 FR[f1].exponent = FP_INTEGER_EXP; 01813 FR[f1].sign = FP_SIGN_POSITIVE; 01814 01815 fp_update_fpsr(sf, tmp_fp_env); 01816 } 01817 fp_update_psr(f1); 01818 } 01819 /* EAS END */ 01820 } 01821 01822 // ****************************************************************** 01823 // _fpcmp 01824 // ****************************************************************** 01825 static INLINE void 01826 _fpcmp(EM_state_type *ps, 01827 EM_opcode_frel_type frel, 01828 EM_opcode_sf_type sf, 01829 EM_uint_t qp, 01830 EM_uint_t f1, 01831 EM_uint_t f2, 01832 EM_uint_t f3) 01833 { 01834 EM_uint_t tmp_isrcode, tmp_res_hi, tmp_res_lo; 01835 EM_fp_reg_type tmp_fr2, tmp_fr3; 01836 EM_tmp_fp_env_type tmp_fp_env; 01837 EM_boolean_t tmp_rel; 01838 01839 /* EAS START */ 01840 if (PR[qp]) { 01841 fp_check_target_register(f1); 01842 if(tmp_isrcode = fp_reg_disabled(f1, f2,f3, 0)) 01843 disabled_fp_register_fault(tmp_isrcode,0); 01844 01845 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3]) ) { 01846 FR[f1] = NATVAL; 01847 } else { 01848 fpcmp_exception_fault_check(f2, f3, frel, sf, &tmp_fp_env); 01849 01850 if (fp_raise_fault(tmp_fp_env)) { 01851 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01852 return; // MACH 01853 } 01854 01855 01856 tmp_fr2 = fp_reg_read_hi(f2); 01857 tmp_fr3 = fp_reg_read_hi(f3); 01858 01859 if (frel == frelEQ) tmp_rel = fp_equal(tmp_fr2, tmp_fr3); 01860 else if (frel == frelLT) tmp_rel = fp_less_than(tmp_fr2, tmp_fr3); 01861 else if (frel == frelLE) tmp_rel = fp_lesser_or_equal(tmp_fr2, tmp_fr3); 01862 else if (frel == frelGT) tmp_rel = fp_less_than(tmp_fr3, tmp_fr2); 01863 else if (frel == frelGE) tmp_rel = fp_lesser_or_equal(tmp_fr3, tmp_fr2); 01864 else if (frel == frelUNORD) tmp_rel = fp_unordered(tmp_fr2, tmp_fr3); 01865 else if (frel == frelNEQ) tmp_rel = !fp_equal(tmp_fr2, tmp_fr3); 01866 else if (frel == frelNLT) tmp_rel = !fp_less_than(tmp_fr2, tmp_fr3); 01867 else if (frel == frelNLE) tmp_rel = !fp_lesser_or_equal(tmp_fr2, tmp_fr3); 01868 else if (frel == frelNGT) tmp_rel = !fp_less_than(tmp_fr3, tmp_fr2); 01869 else if (frel == frelNGE) tmp_rel = !fp_lesser_or_equal(tmp_fr3, tmp_fr2); 01870 else tmp_rel = !fp_unordered(tmp_fr2, tmp_fr3); 01871 01872 tmp_res_hi = (tmp_rel ? 0xFFFFFFFF : 0x00000000); 01873 01874 01875 tmp_fr2 = fp_reg_read_lo(f2); 01876 tmp_fr3 = fp_reg_read_lo(f3); 01877 01878 if (frel == frelEQ) tmp_rel = fp_equal(tmp_fr2, tmp_fr3); 01879 else if (frel == frelLT) tmp_rel = fp_less_than(tmp_fr2, tmp_fr3); 01880 else if (frel == frelLE) tmp_rel = fp_lesser_or_equal(tmp_fr2, tmp_fr3); 01881 else if (frel == frelGT) tmp_rel = fp_less_than(tmp_fr3, tmp_fr2); 01882 else if (frel == frelGE) tmp_rel = fp_lesser_or_equal(tmp_fr3, tmp_fr2); 01883 else if (frel == frelUNORD) tmp_rel = fp_unordered(tmp_fr2, tmp_fr3); 01884 else if (frel == frelNEQ) tmp_rel = !fp_equal(tmp_fr2, tmp_fr3); 01885 else if (frel == frelNLT) tmp_rel = !fp_less_than(tmp_fr2, tmp_fr3); 01886 else if (frel == frelNLE) tmp_rel = !fp_lesser_or_equal(tmp_fr2, tmp_fr3); 01887 else if (frel == frelNGT) tmp_rel = !fp_less_than(tmp_fr3, tmp_fr2); 01888 else if (frel == frelNGE) tmp_rel = !fp_lesser_or_equal(tmp_fr3, tmp_fr2); 01889 else tmp_rel = !fp_unordered(tmp_fr2, tmp_fr3); 01890 01891 tmp_res_lo = (tmp_rel ? 0xFFFFFFFF : 0x00000000); 01892 01893 FR[f1].significand = fp_concatenate(tmp_res_hi, tmp_res_lo); 01894 FR[f1].exponent = FP_INTEGER_EXP; 01895 FR[f1].sign = FP_SIGN_POSITIVE; 01896 01897 fp_update_fpsr(sf, tmp_fp_env); 01898 } 01899 fp_update_psr(f1); 01900 } 01901 /* EAS END */ 01902 } 01903 01904 // ****************************************************************** 01905 // _fcvt_fx 01906 // ****************************************************************** 01907 static INLINE void 01908 _fcvt_fx(EM_state_type *ps, 01909 EM_opcode_sf_type sf, 01910 EM_uint_t qp, 01911 EM_uint_t f1, 01912 EM_uint_t f2) 01913 { 01914 EM_uint_t tmp_isrcode; 01915 EM_fp_reg_type tmp_default_result, tmp_res; 01916 EM_tmp_fp_env_type tmp_fp_env; 01917 01918 /* EAS START */ 01919 if (PR[qp]) { 01920 fp_check_target_register(f1); 01921 if (tmp_isrcode = fp_reg_disabled(f1, f2, 0, 0)) 01922 disabled_fp_register_fault(tmp_isrcode,0); 01923 01924 if (fp_is_natval(FR[f2])) { 01925 FR[f1] = NATVAL; 01926 fp_update_psr(f1); 01927 } else { 01928 tmp_default_result = fcvt_exception_fault_check(f2, sf, 01929 SIGNED_FORM, TRUNC_FORM, &tmp_fp_env); 01930 01931 if (fp_raise_fault(tmp_fp_env)) { 01932 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01933 return; // MACH 01934 } 01935 01936 if (fp_is_nan(tmp_default_result)) { 01937 FR[f1].significand = INTEGER_INDEFINITE; 01938 FR[f1].exponent = FP_INTEGER_EXP; 01939 FR[f1].sign = FP_SIGN_POSITIVE; 01940 } else { 01941 tmp_res = fp_ieee_rnd_to_int(fp_reg_read(FR[f2]), &tmp_fp_env); 01942 if (tmp_res.exponent) 01943 tmp_res.significand = fp_U64_rsh( 01944 tmp_res.significand, FP_INTEGER_EXP - (EM_int_t)tmp_res.exponent); 01945 if (SIGNED_FORM && tmp_res.sign) 01946 tmp_res.significand = (~tmp_res.significand) + 1; 01947 01948 FR[f1].significand = tmp_res.significand; 01949 FR[f1].exponent = FP_INTEGER_EXP; 01950 FR[f1].sign = FP_SIGN_POSITIVE; 01951 } 01952 01953 fp_update_fpsr(sf, tmp_fp_env); 01954 fp_update_psr(f1); 01955 if (fp_raise_traps(tmp_fp_env)) 01956 fp_exception_trap(fp_decode_trap(tmp_fp_env)); 01957 } 01958 } 01959 /* EAS END */ 01960 } 01961 01962 // ****************************************************************** 01963 // _fpcvt_fx 01964 // ****************************************************************** 01965 static INLINE void 01966 _fpcvt_fx(EM_state_type *ps, 01967 EM_opcode_sf_type sf, 01968 EM_uint_t qp, 01969 EM_uint_t f1, 01970 EM_uint_t f2) 01971 { 01972 EM_uint_t tmp_isrcode, tmp_res_lo, tmp_res_hi; 01973 EM_pair_fp_reg_type tmp_default_result_pair; 01974 EM_fp_reg_type tmp_res; 01975 EM_tmp_fp_env_type tmp_fp_env; 01976 01977 /* EAS START */ 01978 if (PR[qp]) { 01979 fp_check_target_register(f1); 01980 if (tmp_isrcode = fp_reg_disabled(f1, f2, 0, 0)) 01981 disabled_fp_register_fault(tmp_isrcode,0); 01982 01983 if (fp_is_natval(FR[f2]) ) { 01984 FR[f1] = NATVAL; 01985 fp_update_psr(f1); 01986 } else { 01987 tmp_default_result_pair = fpcvt_exception_fault_check(f2, sf, 01988 SIGNED_FORM, TRUNC_FORM, &tmp_fp_env); 01989 if (fp_raise_fault(tmp_fp_env)) { 01990 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01991 return; // MACH 01992 } 01993 01994 if (fp_is_nan(tmp_default_result_pair.hi)) { 01995 tmp_res_hi = INTEGER_INDEFINITE_32_BIT; 01996 } else { 01997 tmp_res = fp_ieee_rnd_to_int_sp(fp_reg_read_hi(f2), high, &tmp_fp_env); 01998 if (tmp_res.exponent) 01999 tmp_res.significand = fp_U64_rsh( 02000 tmp_res.significand, (FP_INTEGER_EXP - tmp_res.exponent)); 02001 if (SIGNED_FORM && tmp_res.sign) 02002 tmp_res.significand = (~tmp_res.significand) + 1; 02003 02004 tmp_res_hi = fp_extract_bits(tmp_res.significand, 31, 0); 02005 } 02006 02007 if (fp_is_nan(tmp_default_result_pair.lo)) { 02008 tmp_res_lo = INTEGER_INDEFINITE_32_BIT; 02009 } else { 02010 tmp_res = fp_ieee_rnd_to_int_sp(fp_reg_read_lo(f2), low, &tmp_fp_env); 02011 if (tmp_res.exponent) 02012 tmp_res.significand = fp_U64_rsh( 02013 tmp_res.significand,(FP_INTEGER_EXP - tmp_res.exponent)); 02014 if (SIGNED_FORM && tmp_res.sign) 02015 tmp_res.significand = (~tmp_res.significand) + 1; 02016 02017 tmp_res_lo = fp_extract_bits(tmp_res.significand, 31, 0); 02018 } 02019 FR[f1].significand = fp_concatenate(tmp_res_hi, tmp_res_lo); 02020 FR[f1].exponent = FP_INTEGER_EXP; 02021 FR[f1].sign = FP_SIGN_POSITIVE; 02022 02023 fp_update_fpsr(sf, tmp_fp_env); 02024 fp_update_psr(f1); 02025 if (fp_raise_traps(tmp_fp_env)) 02026 fp_exception_trap(fp_decode_trap(tmp_fp_env)); 02027 } 02028 } 02029 /* EAS END */ 02030 } 02031 02032 02033 /********** fp_ieee_recip **********/ 02034 02035 static EM_fp_reg_type 02036 fp_ieee_recip( 02037 EM_fp_reg_type den) 02038 { 02039 EM_uint_t tmp_index; 02040 EM_fp_reg_type tmp_res; 02041 02042 /* EAS START */ 02043 const EM_uint_t RECIP_TABLE[256] = { 02044 0x3fc, 0x3f4, 0x3ec, 0x3e4, 0x3dd, 0x3d5, 0x3cd, 0x3c6, 02045 0x3be, 0x3b7, 0x3af, 0x3a8, 0x3a1, 0x399, 0x392, 0x38b, 02046 0x384, 0x37d, 0x376, 0x36f, 0x368, 0x361, 0x35b, 0x354, 02047 0x34d, 0x346, 0x340, 0x339, 0x333, 0x32c, 0x326, 0x320, 02048 0x319, 0x313, 0x30d, 0x307, 0x300, 0x2fa, 0x2f4, 0x2ee, 02049 0x2e8, 0x2e2, 0x2dc, 0x2d7, 0x2d1, 0x2cb, 0x2c5, 0x2bf, 02050 0x2ba, 0x2b4, 0x2af, 0x2a9, 0x2a3, 0x29e, 0x299, 0x293, 02051 0x28e, 0x288, 0x283, 0x27e, 0x279, 0x273, 0x26e, 0x269, 02052 0x264, 0x25f, 0x25a, 0x255, 0x250, 0x24b, 0x246, 0x241, 02053 0x23c, 0x237, 0x232, 0x22e, 0x229, 0x224, 0x21f, 0x21b, 02054 0x216, 0x211, 0x20d, 0x208, 0x204, 0x1ff, 0x1fb, 0x1f6, 02055 0x1f2, 0x1ed, 0x1e9, 0x1e5, 0x1e0, 0x1dc, 0x1d8, 0x1d4, 02056 0x1cf, 0x1cb, 0x1c7, 0x1c3, 0x1bf, 0x1bb, 0x1b6, 0x1b2, 02057 0x1ae, 0x1aa, 0x1a6, 0x1a2, 0x19e, 0x19a, 0x197, 0x193, 02058 0x18f, 0x18b, 0x187, 0x183, 0x17f, 0x17c, 0x178, 0x174, 02059 0x171, 0x16d, 0x169, 0x166, 0x162, 0x15e, 0x15b, 0x157, 02060 0x154, 0x150, 0x14d, 0x149, 0x146, 0x142, 0x13f, 0x13b, 02061 0x138, 0x134, 0x131, 0x12e, 0x12a, 0x127, 0x124, 0x120, 02062 0x11d, 0x11a, 0x117, 0x113, 0x110, 0x10d, 0x10a, 0x107, 02063 0x103, 0x100, 0x0fd, 0x0fa, 0x0f7, 0x0f4, 0x0f1, 0x0ee, 02064 0x0eb, 0x0e8, 0x0e5, 0x0e2, 0x0df, 0x0dc, 0x0d9, 0x0d6, 02065 0x0d3, 0x0d0, 0x0cd, 0x0ca, 0x0c8, 0x0c5, 0x0c2, 0x0bf, 02066 0x0bc, 0x0b9, 0x0b7, 0x0b4, 0x0b1, 0x0ae, 0x0ac, 0x0a9, 02067 0x0a6, 0x0a4, 0x0a1, 0x09e, 0x09c, 0x099, 0x096, 0x094, 02068 0x091, 0x08e, 0x08c, 0x089, 0x087, 0x084, 0x082, 0x07f, 02069 0x07c, 0x07a, 0x077, 0x075, 0x073, 0x070, 0x06e, 0x06b, 02070 0x069, 0x066, 0x064, 0x061, 0x05f, 0x05d, 0x05a, 0x058, 02071 0x056, 0x053, 0x051, 0x04f, 0x04c, 0x04a, 0x048, 0x045, 02072 0x043, 0x041, 0x03f, 0x03c, 0x03a, 0x038, 0x036, 0x033, 02073 0x031, 0x02f, 0x02d, 0x02b, 0x029, 0x026, 0x024, 0x022, 02074 0x020, 0x01e, 0x01c, 0x01a, 0x018, 0x015, 0x013, 0x011, 02075 0x00f, 0x00d, 0x00b, 0x009, 0x007, 0x005, 0x003, 0x001, 02076 }; 02077 02078 02079 tmp_index = fp_extract_bits(den.significand,62,55); 02080 tmp_res.significand = ((EM_uint64_t)1 << 63) | ((EM_uint64_t)RECIP_TABLE[tmp_index] << 53); 02081 tmp_res.exponent = (EM_int_t)FP_REG_EXP_ONES - 2 - (EM_int_t)den.exponent; 02082 tmp_res.sign = den.sign; 02083 return (tmp_res); 02084 02085 /* EAS END */ 02086 } 02087 02088 02089 /********** fp_ieee_recip_sqrt **********/ 02090 02091 static EM_fp_reg_type 02092 fp_ieee_recip_sqrt( 02093 EM_fp_reg_type root) 02094 { 02095 EM_uint_t tmp_index; 02096 EM_fp_reg_type tmp_res; 02097 02098 /* EAS START */ 02099 const EM_uint_t RECIP_SQRT_TABLE[256] = { 02100 0x1a5, 0x1a0, 0x19a, 0x195, 0x18f, 0x18a, 0x185, 0x180, 02101 0x17a, 0x175, 0x170, 0x16b, 0x166, 0x161, 0x15d, 0x158, 02102 0x153, 0x14e, 0x14a, 0x145, 0x140, 0x13c, 0x138, 0x133, 02103 0x12f, 0x12a, 0x126, 0x122, 0x11e, 0x11a, 0x115, 0x111, 02104 0x10d, 0x109, 0x105, 0x101, 0x0fd, 0x0fa, 0x0f6, 0x0f2, 02105 0x0ee, 0x0ea, 0x0e7, 0x0e3, 0x0df, 0x0dc, 0x0d8, 0x0d5, 02106 0x0d1, 0x0ce, 0x0ca, 0x0c7, 0x0c3, 0x0c0, 0x0bd, 0x0b9, 02107 0x0b6, 0x0b3, 0x0b0, 0x0ad, 0x0a9, 0x0a6, 0x0a3, 0x0a0, 02108 0x09d, 0x09a, 0x097, 0x094, 0x091, 0x08e, 0x08b, 0x088, 02109 0x085, 0x082, 0x07f, 0x07d, 0x07a, 0x077, 0x074, 0x071, 02110 0x06f, 0x06c, 0x069, 0x067, 0x064, 0x061, 0x05f, 0x05c, 02111 0x05a, 0x057, 0x054, 0x052, 0x04f, 0x04d, 0x04a, 0x048, 02112 0x045, 0x043, 0x041, 0x03e, 0x03c, 0x03a, 0x037, 0x035, 02113 0x033, 0x030, 0x02e, 0x02c, 0x029, 0x027, 0x025, 0x023, 02114 0x020, 0x01e, 0x01c, 0x01a, 0x018, 0x016, 0x014, 0x011, 02115 0x00f, 0x00d, 0x00b, 0x009, 0x007, 0x005, 0x003, 0x001, 02116 0x3fc, 0x3f4, 0x3ec, 0x3e5, 0x3dd, 0x3d5, 0x3ce, 0x3c7, 02117 0x3bf, 0x3b8, 0x3b1, 0x3aa, 0x3a3, 0x39c, 0x395, 0x38e, 02118 0x388, 0x381, 0x37a, 0x374, 0x36d, 0x367, 0x361, 0x35a, 02119 0x354, 0x34e, 0x348, 0x342, 0x33c, 0x336, 0x330, 0x32b, 02120 0x325, 0x31f, 0x31a, 0x314, 0x30f, 0x309, 0x304, 0x2fe, 02121 0x2f9, 0x2f4, 0x2ee, 0x2e9, 0x2e4, 0x2df, 0x2da, 0x2d5, 02122 0x2d0, 0x2cb, 0x2c6, 0x2c1, 0x2bd, 0x2b8, 0x2b3, 0x2ae, 02123 0x2aa, 0x2a5, 0x2a1, 0x29c, 0x298, 0x293, 0x28f, 0x28a, 02124 0x286, 0x282, 0x27d, 0x279, 0x275, 0x271, 0x26d, 0x268, 02125 0x264, 0x260, 0x25c, 0x258, 0x254, 0x250, 0x24c, 0x249, 02126 0x245, 0x241, 0x23d, 0x239, 0x235, 0x232, 0x22e, 0x22a, 02127 0x227, 0x223, 0x220, 0x21c, 0x218, 0x215, 0x211, 0x20e, 02128 0x20a, 0x207, 0x204, 0x200, 0x1fd, 0x1f9, 0x1f6, 0x1f3, 02129 0x1f0, 0x1ec, 0x1e9, 0x1e6, 0x1e3, 0x1df, 0x1dc, 0x1d9, 02130 0x1d6, 0x1d3, 0x1d0, 0x1cd, 0x1ca, 0x1c7, 0x1c4, 0x1c1, 02131 0x1be, 0x1bb, 0x1b8, 0x1b5, 0x1b2, 0x1af, 0x1ac, 0x1aa, 02132 }; 02133 02134 tmp_index = (fp_extract_bits((EM_uint64_t)root.exponent,0,0) << 7) | 02135 fp_extract_bits(root.significand,62,56); 02136 02137 tmp_res.significand = ((EM_uint64_t)1 << 63) |((EM_uint64_t)RECIP_SQRT_TABLE[tmp_index] << 53); 02138 tmp_res.exponent = ((EM_int_t)FP_REG_EXP_HALF) - ((((EM_int_t)root.exponent) - ((EM_int_t)FP_REG_BIAS)) >> 1); 02139 tmp_res.sign = FP_SIGN_POSITIVE; 02140 return(tmp_res); 02141 02142 /* EAS END */ 02143 }