00001 /***************************************************************************** 00002 * 00003 * (C) Copyright MICROSOFT Corp., 1996 00004 * 00005 * Title: ACPITABL.H --- Definitions and descriptions of the various BIOS supplied ACPI tables. 00006 * 00007 * Version: 1.00 00008 * 00009 * Date: 6-17-96 00010 * 00011 * Author: Jason Clark (jasoncl) 00012 * 00013 *------------------------------------------------------------------------------ 00014 * 00015 * Change log: 00016 * 00017 * DATE REV DESCRIPTION 00018 * ----------- --- ----------------------------------------------------------- 00019 * 00020 ****************************************************************************/ 00021 00022 // These map to bios provided structures, so turn on 1 byte packing 00023 00024 #include <pshpack1.h> 00025 00026 #define RSDP_SIGNATURE 0x2052545020445352 // "RSD PTR " 00027 00028 typedef struct _RSDP { // Root System Description Table Pointer Structure 00029 00030 ULONGLONG Signature; // 8 UCHAR table signature 'RSD PTR ' 00031 UCHAR Checksum; // sum of all UCHARs of structure must = 0 00032 UCHAR OEMID[6]; // String that uniquely ID's the OEM 00033 UCHAR Reserved[1]; // must be 0 00034 ULONG RsdtAddress; // physical address of Root System Description Table 00035 00036 } RSDP; 00037 00038 typedef RSDP *PRSDP; 00039 00040 #ifndef NEC_98 00041 #define RSDP_SEARCH_RANGE_BEGIN 0xE0000 // physical address where we begin searching for the RSDP 00042 #else // NEC_98 00043 #define RSDP_SEARCH_RANGE_BEGIN 0xE8000 // physical address where we begin searching for the RSDP 00044 #endif // NEC_98 00045 #define RSDP_SEARCH_RANGE_END 0xFFFFF 00046 #define RSDP_SEARCH_RANGE_LENGTH (RSDP_SEARCH_RANGE_END-RSDP_SEARCH_RANGE_BEGIN+1) 00047 #define RSDP_SEARCH_INTERVAL 16 // search on 16 byte boundaries 00048 00049 typedef struct _DESCRIPTION_HEADER { // Header structure appears at the beginning of each ACPI table 00050 00051 ULONG Signature; // Signature used to identify the type of table 00052 ULONG Length; // Length of entire table including the DESCRIPTION_HEADER 00053 UCHAR Revision; // Minor version of ACPI spec to which this table conforms 00054 UCHAR Checksum; // sum of all bytes in the entire TABLE should = 0 00055 UCHAR OEMID[6]; // String that uniquely ID's the OEM 00056 UCHAR OEMTableID[8]; // String that uniquely ID's this table (used for table patching and replacement). 00057 ULONG OEMRevision; // OEM supplied table revision number. Bigger number = newer table. 00058 UCHAR CreatorID[4]; // Vendor ID of utility which created this table. 00059 ULONG CreatorRev; // Revision of utility that created the table. 00060 00061 } DESCRIPTION_HEADER; 00062 00063 typedef DESCRIPTION_HEADER *PDESCRIPTION_HEADER; 00064 00065 // Header constants 00066 00067 #define ACPI_MAX_SIGNATURE 4 00068 #define ACPI_MAX_OEM_ID 6 00069 #define ACPI_MAX_TABLE_ID 8 00070 #define ACPI_MAX_TABLE_STRINGS ACPI_MAX_SIGNATURE + ACPI_MAX_OEM_ID + ACPI_MAX_TABLE_ID 00071 00072 #define FACS_SIGNATURE 0x53434146 // "FACS" 00073 00074 typedef struct _FACS { // Firmware ACPI Control Structure. Note that this table does not have a header, it is pointed to by the FADT 00075 00076 ULONG Signature; // 'FACS' 00077 ULONG Length; // Length of entire firmware ACPI control structure (must be 64 bytes or larger) 00078 ULONG HardwareSignature; 00079 ULONG pFirmwareWakingVector; // physical address of location where the OS needs to put the firmware waking vector 00080 ULONG GlobalLock; // 32 bit structure used for sharing Embedded Controller 00081 ULONG Flags; 00082 UCHAR Reserved[40]; 00083 } FACS; 00084 00085 typedef FACS *PFACS; 00086 00087 // FACS.GlobalLock bit field definitions 00088 00089 #define GL_PENDING_BIT 0x00 00090 #define GL_PENDING (1 << GL_PENDING_BIT) 00091 00092 #define GL_OWNER_BIT 0x01 00093 #define GL_OWNER (1 << GL_OWNER_BIT) 00094 00095 #define GL_NON_RESERVED_BITS_MASK (GL_PENDING+GL_OWNED) 00096 00097 // Generic Register Address Structure 00098 00099 typedef struct _GEN_ADDR { 00100 UCHAR AddressSpaceID; 00101 UCHAR BitWidth; 00102 UCHAR BitOffset; 00103 UCHAR Reserved; 00104 PHYSICAL_ADDRESS Address; 00105 } GEN_ADDR, *PGEN_ADDR; 00106 00107 // FACS Flags definitions 00108 00109 #define FACS_S4BIOS_SUPPORTED_BIT 0 // flag indicates whether or not the BIOS will save/restore memory around S4 00110 #define FACS_S4BIOS_SUPPORTED (1 << FACS_S4BIOS_SUPPORTED_BIT) 00111 00112 00113 #define FADT_SIGNATURE 0x50434146 // "FACP" 00114 00115 typedef struct _FADT { // Fixed ACPI description table 00116 00117 DESCRIPTION_HEADER Header; 00118 ULONG facs; // Physical address of the Firmware ACPI Control Structure 00119 ULONG dsdt; // Physical address of the Differentiated System Description Table 00120 UCHAR int_model; // System's Interrupt mode, 0=Dual PIC, 1=Multiple APIC, >1 reserved 00121 UCHAR reserved4; 00122 USHORT sci_int_vector; // Vector of SCI interrupt. 00123 ULONG smi_cmd_io_port; // Address in System I/O Space of the SMI Command port, used to enable and disable ACPI. 00124 UCHAR acpi_on_value; // Value out'd to smi_cmd_port to activate ACPI 00125 UCHAR acpi_off_value; // Value out'd to smi_cmd_port to deactivate ACPI 00126 UCHAR s4bios_req; // Value to write to SMI_CMD to enter the S4 state. 00127 UCHAR reserved1; // Must Be 0 00128 ULONG pm1a_evt_blk_io_port; // Address in System I/O Space of the PM1a_EVT_BLK register block 00129 ULONG pm1b_evt_blk_io_port; // Address in System I/O Space of the PM1b_EVT_BLK register block 00130 ULONG pm1a_ctrl_blk_io_port; // Address in System I/O Space of the PM1a_CNT_BLK register block 00131 ULONG pm1b_ctrl_blk_io_port; // Address in System I/O Space of the PM1b_CNT_BLK register block 00132 ULONG pm2_ctrl_blk_io_port; // Address in System I/O Space of the PM2_CNT_BLK register block 00133 ULONG pm_tmr_blk_io_port; // Address in System I/O Space of the PM_TMR register block 00134 ULONG gp0_blk_io_port; // Address in System I/O Space of the GP0 register block 00135 ULONG gp1_blk_io_port; // Address in System I/O Space of the GP1 register block 00136 UCHAR pm1_evt_len; // number of bytes decoded for PM1_BLK (must be >= 4) 00137 UCHAR pm1_ctrl_len; // number of bytes decoded for PM1_CNT (must be >= 2) 00138 UCHAR pm2_ctrl_len; // number of bytes decoded for PM1a_CNT (must be >= 1) 00139 UCHAR pm_tmr_len; // number of bytes decoded for PM_TMR (must be >= 4) 00140 UCHAR gp0_blk_len; // number of bytes decoded for GP0_BLK (must be multiple of 2) 00141 UCHAR gp1_blk_len; // number of bytes decoded for GP1_BLK (must be multiple of 2) 00142 UCHAR gp1_base; // index at which GP1 based events start 00143 UCHAR reserved2; // Must Be 0 00144 USHORT lvl2_latency; // Worst case latency in microseconds required to enter and leave the C2 processor state 00145 USHORT lvl3_latency; // Worst case latency in microseconds required to enter and leave the C3 processor state 00146 USHORT flush_size; // Ignored if WBINVD flag is 1 -- indicates size of memory read to flush dirty lines from 00147 // any processors memory caches. A size of zero indicates this is not supported. 00148 USHORT flush_stride; // Ignored if WBINVD flag is 1 -- the memory stride width, in bytes, to perform reads to flush 00149 // the processor's memory caches. 00150 UCHAR duty_offset; // zero based index of where the processor's duty cycle setting is within the processor's P_CNT register. 00151 UCHAR duty_width; // bit width of the processor's duty cycle setting value in the P_CNT register. 00152 // a value of zero indicates that processor duty cycle is not supported 00153 UCHAR day_alarm_index; 00154 UCHAR month_alarm_index; 00155 UCHAR century_alarm_index; 00156 USHORT boot_arch; 00157 UCHAR reserved3[1]; 00158 ULONG flags; 00159 GEN_ADDR reset_reg; 00160 UCHAR reset_val; 00161 00162 } FADT; 00163 00164 typedef FADT *PFADT; 00165 00166 // definition of FADT.flags bits 00167 00168 // this one bit flag indicates whether or not the WBINVD instruction works properly,if this bit is not set we can not use S2, S3 states, or 00169 // C3 on MP machines 00170 #define WRITEBACKINVALIDATE_WORKS_BIT 0 00171 #define WRITEBACKINVALIDATE_WORKS (1 << WRITEBACKINVALIDATE_WORKS_BIT) 00172 00173 // this flag indicates if wbinvd works EXCEPT that it does not invalidate the cache 00174 #define WRITEBACKINVALIDATE_DOESNT_INVALIDATE_BIT 1 00175 #define WRITEBACKINVALIDATE_DOESNT_INVALIDATE (1 << WRITEBACKINVALIDATE_DOESNT_INVALIDATE_BIT) 00176 00177 // this flag indicates that the C1 state is supported on all processors. 00178 #define SYSTEM_SUPPORTS_C1_BIT 2 00179 #define SYSTEM_SUPPORTS_C1 (1 << SYSTEM_SUPPORTS_C1_BIT) 00180 00181 // this one bit flag indicates whether support for the C2 state is restricted to uniprocessor machines 00182 #define P_LVL2_UP_ONLY_BIT 3 00183 #define P_LVL2_UP_ONLY (1 << P_LVL2_UP_ONLY_BIT) 00184 00185 // this bit indicates whether the PWR button is treated as a fix feature (0) or a generic feature (1) 00186 #define PWR_BUTTON_GENERIC_BIT 4 00187 #define PWR_BUTTON_GENERIC (1 << PWR_BUTTON_GENERIC_BIT) 00188 00189 #define SLEEP_BUTTON_GENERIC_BIT 5 00190 #define SLEEP_BUTTON_GENERIC (1 << SLEEP_BUTTON_GENERIC_BIT) 00191 00192 // this bit indicates whether the RTC wakeup status is reported in fix register space (0) or not (1) 00193 #define RTC_WAKE_GENERIC_BIT 6 00194 #define RTC_WAKE_GENERIC (1 << RTC_WAKE_GENERIC_BIT) 00195 00196 #define RTC_WAKE_FROM_S4_BIT 7 00197 #define RTC_WAKE_FROM_S4 (1 << RTC_WAKE_FROM_S4_BIT) 00198 00199 // This bit indicates whether the machine implements a 24 or 32 bit timer. 00200 #define TMR_VAL_EXT_BIT 8 00201 #define TMR_VAL_EXT (1 << TMR_VAL_EXT_BIT) 00202 00203 // This bit indicates whether the machine supports docking 00204 #define DCK_CAP_BIT 9 00205 #define DCK_CAP (1 << DCK_CAP_BIT) 00206 00207 // This bit indicates whether the machine supports reset 00208 #define RESET_CAP_BIT 10 00209 #define RESET_CAP (1 << RESET_CAP_BIT) 00210 00211 // spec defines maximum entry/exit latency values for C2 and C3, if the FADT indicates that these values are 00212 // exceeded then we do not use that C state. 00213 00214 #define C2_MAX_LATENCY 100 00215 #define C3_MAX_LATENCY 1000 00216 00217 // 00218 // Definition of FADT.boot_arch flags 00219 // 00220 00221 #define LEGACY_DEVICES 1 00222 #define I8042 2 00223 00224 00225 #ifndef ANYSIZE_ARRAY 00226 #define ANYSIZE_ARRAY 1 00227 #endif 00228 00229 // Multiple APIC description table 00230 00231 typedef struct _MAPIC { 00232 00233 DESCRIPTION_HEADER Header; 00234 ULONG LocalAPICAddress; // Physical Address at which each processor can access its local APIC 00235 ULONG Flags; 00236 ULONG APICTables[ANYSIZE_ARRAY]; // A list of APIC tables. 00237 00238 } MAPIC; 00239 00240 typedef MAPIC *PMAPIC; 00241 00242 // Multiple APIC structure flags 00243 00244 #define PCAT_COMPAT_BIT 0 // indicates that the system also has a dual 8259 pic setup. 00245 #define PCAT_COMPAT (1 << PCAT_COMPAT_BIT) 00246 00247 // APIC Structure Types 00248 #define PROCESSOR_LOCAL_APIC 0 00249 #define IO_APIC 1 00250 #define ISA_VECTOR_OVERRIDE 2 00251 #define IO_NMI_SOURCE 3 00252 #define LOCAL_NMI_SOURCE 4 00253 #define PROCESSOR_LOCAL_APIC_LENGTH 8 00254 #define IO_APIC_LENGTH 12 00255 #define ISA_VECTOR_OVERRIDE_LENGTH 10 00256 #define IO_NMI_SOURCE_LENGTH 8 00257 #define LOCAL_NMI_SOURCE_LENGTH 6 00258 00259 // These defines come from the MPS 1.4 spec, section 4.3.4 and they are referenced as 00260 // such in the ACPI spec. 00261 #define PO_BITS 3 00262 #define POLARITY_HIGH 1 00263 #define POLARITY_LOW 3 00264 #define POLARITY_CONFORMS_WITH_BUS 0 00265 #define EL_BITS 0xc 00266 #define EL_BIT_SHIFT 2 00267 #define EL_EDGE_TRIGGERED 4 00268 #define EL_LEVEL_TRIGGERED 0xc 00269 #define EL_CONFORMS_WITH_BUS 0 00270 00271 // The shared beginning info in all APIC Structures 00272 00273 typedef struct _APICTABLE { 00274 UCHAR Type; 00275 UCHAR Length; 00276 } APICTABLE; 00277 00278 typedef APICTABLE *PAPICTABLE; 00279 00280 typedef struct _PROCLOCALAPIC { 00281 00282 UCHAR Type; // should be zero to identify a ProcessorLocalAPIC structure 00283 UCHAR Length; // better be 8 00284 UCHAR ACPIProcessorID; // ProcessorID for which this processor is listed in the ACPI processor declaration 00285 // operator. 00286 UCHAR APICID; // The processor's local APIC ID. 00287 ULONG Flags; 00288 00289 } PROCLOCALAPIC; 00290 00291 typedef PROCLOCALAPIC *PPROCLOCALAPIC; 00292 00293 // Processor Local APIC Flags 00294 #define PLAF_ENABLED_BIT 0 00295 #define PLAF_ENABLED (1 << PLAF_ENABLED_BIT) 00296 00297 typedef struct _IOAPIC { 00298 00299 UCHAR Type; 00300 UCHAR Length; // better be 12 00301 UCHAR IOAPICID; 00302 UCHAR Reserved; 00303 ULONG IOAPICAddress; // Physical address at which this IO APIC resides. 00304 ULONG SystemVectorBase; // system interrupt vector index for this APIC 00305 00306 } IOAPIC; 00307 00308 typedef IOAPIC *PIOAPIC; 00309 00310 // Interrupt Source Override 00311 typedef struct { 00312 UCHAR Type; // Must be 2 00313 UCHAR Length; // Must be 10 00314 UCHAR Bus; // Must be 0 00315 UCHAR Source; // BusRelative IRQ 00316 ULONG GlobalSystemInterruptVector; // Global IRQ 00317 USHORT Flags; // Same as MPS INTI Flags 00318 } ISA_VECTOR, *PISA_VECTOR; 00319 00320 // I/O Non-Maskable Source Interrupt 00321 typedef struct { 00322 UCHAR Type; // must be 3 00323 UCHAR Length; // better be 8 00324 USHORT Flags; // Same as MPS INTI Flags 00325 ULONG GlobalSystemInterruptVector; // Interrupt connected to NMI 00326 } IO_NMISOURCE, *PIO_NMISOURCE; 00327 00328 // Local Non-Maskable Interrupt Source 00329 typedef struct { 00330 UCHAR Type; // must be 4 00331 UCHAR Length; // better be 6 00332 UCHAR ProcessorID; // which processor? 0xff means all 00333 USHORT Flags; 00334 UCHAR LINTIN; // which LINTIN# signal on the processor 00335 } LOCAL_NMISOURCE, *PLOCAL_NMISOURCE; 00336 00337 typedef struct _SMARTBATTTABLE { 00338 00339 DESCRIPTION_HEADER Header; 00340 ULONG WarningEnergyLevel; // mWh at which the OEM suggests we warn the user that the battery is getting low. 00341 ULONG LowEnergyLevel; // mWh at which the OEM suggests we put the machine into a sleep state. 00342 ULONG CriticalEnergyLevel; // mWH at which the OEM suggests we do an emergency shutdown. 00343 00344 } SMARTBATTTABLE; 00345 00346 typedef SMARTBATTTABLE *PSMARTBATTTABLE; 00347 00348 #define RSDT_SIGNATURE 0x54445352 // "RSDT" 00349 00350 typedef struct _RSDT { // Root System Description Table 00351 00352 DESCRIPTION_HEADER Header; 00353 ULONG Tables[ANYSIZE_ARRAY]; // The structure contains an n length array of physical addresses each of which point to another table. 00354 00355 } RSDT; 00356 00357 typedef RSDT *PRSDT; 00358 00359 // The below macro uses the min macro to protect against the case where we are running on machine which is compliant with 00360 // a spec prior to .99. If you had a .92 compliant header and one table pointer we would end of subtracting 32-36 resulting 00361 // in a really big number and hence we would think we had lots and lots of tables... Using the min macro we end up subtracting 00362 // the length-length getting zero which will be harmless and cause us to fail to load (with a red screen on Win9x) which is 00363 // the best we can do in this case. 00364 00365 #ifndef min 00366 #define min(a,b) (((a) < (b)) ? (a) : (b)) 00367 #endif 00368 00369 #define NumTableEntriesFromRSDTPointer(p) (p->Header.Length-min(p->Header.Length,sizeof(DESCRIPTION_HEADER)))/4 00370 00371 00372 #define APIC_SIGNATURE 0x43495041 // "APIC" 00373 #define DSDT_SIGNATURE 0x54445344 // "DSDT" 00374 #define SSDT_SIGNATURE 0x54445353 // "SSDT" 00375 #define PSDT_SIGNATURE 0x54445350 // "PSDT" 00376 #define SBST_SIGNATURE 0x54534253 // "SBST" 00377 #define DBGP_SIGNATURE 0x50474244 // "DBGP" 00378 00379 typedef struct _DSDT { // Differentiated System Description Table 00380 00381 DESCRIPTION_HEADER Header; 00382 UCHAR DiffDefBlock[ANYSIZE_ARRAY]; // this is the AML describing the base system. 00383 00384 } DSDT; 00385 00386 typedef DSDT *PDSDT; 00387 00388 // Resume normal structure packing 00389 00390 #include <poppack.h> 00391 00392 typedef struct { 00393 UCHAR NamespaceProcID; 00394 UCHAR ApicID; 00395 UCHAR NtNumber; 00396 BOOLEAN Started; 00397 BOOLEAN Enumerated; 00398 } PROC_LOCAL_APIC, *PPROC_LOCAL_APIC; 00399 00400 extern PROC_LOCAL_APIC HalpProcLocalApicTable[]; 00401 00402 // 00403 // Debug Port Table 00404 // 00405 00406 typedef struct _DEBUG_PORT_TABLE { 00407 00408 DESCRIPTION_HEADER Header; 00409 UCHAR InterfaceType; 00410 UCHAR Reserved[3]; 00411 GEN_ADDR BaseAddress; 00412 } DEBUG_PORT_TABLE, *PDEBUG_PORT_TABLE; 00413
1.3.7