test: ia32def.h Source File

00001 /*++ 00002 00003 Module Name: 00004 00005 iA32DEF.H 00006 00007 Abstract: 00008 00009 This file defines iA32 macros for iA32Trap.c and Opcode Emulation use 00010 00011 Author: 00012 00013 00014 Environment: 00015 00016 Kernel mode only. 00017 00018 Revision History: 00019 00020 --*/ 00021 00022 #define KERNELONLY 1 00023 // #include ks386.inc 00024 // #include callconv.inc // calling convention macros 00025 // #include i386\kimacro.inc 00026 // #include mac386.inc 00027 // #include i386\mi.inc 00028 00029 00030 // 00031 // Equates for exceptions which cause system fatal error 00032 // 00033 00034 #define EXCEPTION_DIVIDED_BY_ZERO 0 00035 #define EXCEPTION_DEBUG 1 00036 #define EXCEPTION_NMI 2 00037 #define EXCEPTION_INT3 3 00038 #define EXCEPTION_BOUND_CHECK 5 00039 #define EXCEPTION_INVALID_OPCODE 6 00040 #define EXCEPTION_NPX_NOT_AVAILABLE 7 00041 #define EXCEPTION_DOUBLE_FAULT 8 00042 #define EXCEPTION_NPX_OVERRUN 9 00043 #define EXCEPTION_INVALID_TSS 0x0A 00044 #define EXCEPTION_SEGMENT_NOT_PRESENT 0x0B 00045 #define EXCEPTION_STACK_FAULT 0x0C 00046 #define EXCEPTION_GP_FAULT 0x0D 00047 #define EXCEPTION_RESERVED_TRAP 0x0F 00048 #define EXCEPTION_NPX_ERROR 0x010 00049 #define EXCEPTION_ALIGNMENT_CHECK 0x011 00050 00051 #define BREAKPOINT_BREAK 0x00 00052 // 00053 // Exception flags 00054 // 00055 00056 #define EXCEPT_UNKNOWN_ACCESS 0 00057 #define EXCEPT_LIMIT_ACCESS 0x10 00058 00059 // 00060 // page fault read/write mask 00061 // 00062 00063 #define ERR_0E_STORE 2 00064 00065 // 00066 // Debug register 6 (dr6) BS (single step) bit mask 00067 // 00068 00069 #define DR6_BS_MASK 0x4000 00070 00071 // 00072 // EFLAGS single step bit 00073 // 00074 00075 #define EFLAGS_TF_BIT 0x100 00076 #define EFLAGS_OF_BIT 0x4000 00077 00078 // 00079 // The mask of selecot's table indicator (ldt or gdt) 00080 // 00081 00082 #define TABLE_INDICATOR_MASK 4 00083 00084 // 00085 // Opcode for Pop SegReg and iret instructions 00086 // 00087 00088 #define POP_DS 0x01F 00089 #define POP_ES 0x07 00090 #define POP_FS 0x0A10F 00091 #define POP_GS 0x0A90F 00092 #define IRET_OP 0x0CF 00093 #define CLI_OP 0x0FA 00094 #define STI_OP 0x0FB 00095 #define PUSHF_OP 0x09C 00096 #define POPF_OP 0x09D 00097 #define INTNN_OP 0x00CD 00098 #define FRSTOR_ECX 0x0021DD9B 00099 #define FWAIT_OP 0x009b 00100 00101 00102 #define GATE_TYPE_386INT 0x0E00 00103 #define GATE_TYPE_386TRAP 0x0F00 00104 #define GATE_TYPE_TASK 0x0500 00105 #define D_GATE 0 00106 #define D_PRESENT 0x08000 00107 #define D_DPL_3 0x06000 00108 #define D_DPL_0 0 00109 00110 // 00111 // Definitions for present 386 trap and interrupt gate attributes 00112 // 00113 00114 #define D_TRAP032 D_PRESENT+D_DPL_0+D_GATE+GATE_TYPE_386TRAP 00115 #define D_TRAP332 D_PRESENT+D_DPL_3+D_GATE+GATE_TYPE_386TRAP 00116 #define D_INT032 D_PRESENT+D_DPL_0+D_GATE+GATE_TYPE_386INT 00117 #define D_INT332 D_PRESENT+D_DPL_3+D_GATE+GATE_TYPE_386INT 00118 #define D_TASK D_PRESENT+D_DPL_0+D_GATE+GATE_TYPE_TASK 00119 00120 // 00121 // Bit patterns for Intercept_Code or Trap_Code, 00122 // patterns used in IIM on IA32 trap 00123 // 00124 #define TRAPCODE_TB 0x0004 // taken branch trap 00125 #define TRAPCODE_SS 0x0008 // single step trap 00126 #define TRAPCODE_B0 0x0010 // Data breakpoint trap 00127 #define TRAPCODE_B1 0x0020 00128 #define TRAPCODE_B2 0x0040 00129 #define TRAPCODE_B3 0x0080 00130 00131 #define INTERCEPT_OS 0x0002 // Operand size 00132 #define INTERCEPT_AS 0x0004 // Address size 00133 #define INTERCEPT_LP 0x0008 // Lock Prefix 00134 #define INTERCEPT_RP 0x0010 // REP prefix 00135 #define INTERCEPT_NP 0x0020 // REPNE prefix 00136 #define INTERCEPT_SP 0x0040 // Segment prefix 00137 #define INTERCEPT_SEG 0x0380 // Segment valuse 00138 #define INTERCEPT_0F 0x0400 // 0F opcode series 00139 00140 #define HARDWARE_VM 0x0800 // VM86 mode 00141 #define HARDWARE_RM 0x1000 // Real Mode 00142 #define HARDWARE_PM 0x2000 // Protect Mode 00143 #define HARDWARE_SS 0x4000 // Stack size, 32 or 16 bits 00144 #define HARDWARE_UR 0x8000 // User or privileged mode 00145 00146 // 00147 // Following MI_*** definitions are created from MI386.INC 00148 // 00149 #define MAX_INSTRUCTION_LENGTH 15 00150 #define MAX_INSTRUCTION_PREFIX_LENGTH 4 00151 #define MI_LOCK_PREFIX 0x0F0 00152 #define MI_ADDR_PREFIX 0x067 00153 #define MI_TWO_BYTE 0x0F 00154 #define MI_HLT 0x0F4 00155 #define MI_LTR_LLDT 0 00156 #define MI_LGDT_LIDT_LMSW 0x01 00157 #define MI_MODRM_MASK 0x38 00158 #define MI_LLDT_MASK 0x10 00159 #define MI_LTR_MASK 0x18 00160 #define MI_LGDT_MASK 0x10 00161 #define MI_LIDT_MASK 0x18 00162 #define MI_LMSW_MASK 0x30 00163 #define MI_SPECIAL_MOV_MASK 0x20 00164 #define MI_REP_INS_OUTS 0x0F3 00165 #define MI_MIN_INS_OUTS 0x06C 00166 #define MI_MAX_INS_OUTS 0x06F 00167 #define MI_LMSW_OPCODE 0x001 // second byte of lmsw 00168 #define MI_CLTS_OPCODE 0x006 // second byte of clts 00169 #define MI_GET_CRx_OPCODE 0x020 // mov r32,CRx 00170 #define MI_SET_CRx_OPCODE 0x022 // mov CRx,r32 00171 #define MI_GET_TRx_OPCODE 0x024 // mov r32,TRx 00172 #define MI_SET_TRx_OPCODE 0x026 // mov TRx,r32 00173 #define MI_REGMASK 0x038 // REG field mask 00174 #define MI_REGSHIFT 0x3 // REG field shift 00175 #define MI_REGLMSW 0x030 // REG field for lmsw 00176 #define MI_MODMASK 0x0C0 // MOD field mask 00177 #define MI_MODSHIFT 0x6 // MOD field shift 00178 #define MI_MODMOVSPEC 0x0C0 // MOD field for mov to/from special 00179 #define MI_MODNONE 0 00180 #define MI_RMMASK 0x007 // RM field mask 00181 #define MI_RMBP 0x006 // RM value for bp reg 00182 #define MI_RMSIB 0x004 // RM value for sib 00183 00184 #define MI_SIB_BASEMASK 0x007 // SIB BASE field mask 00185 #define MI_SIB_BASENONE 0x005 00186 #define MI_SIB_BASESHIFT 0 00187 00188 #define MI_SIB_INDEXMASK 0x038 00189 #define MI_SIB_INDEXSHIFT 3 00190 #define MI_SIB_INDEXNONE 0x020 00191 00192 #define MI_SIB_SSMASK 0x0c0 00193 #define MI_SIB_SSSHIFT 0x6 00194 00195 // 00196 // definition for floating status word error mask 00197 // 00198 00199 #define FSW_INVALID_OPERATION 0x0001 00200 #define FSW_DENORMAL 0x0002 00201 #define FSW_ZERO_DIVIDE 0x0004 00202 #define FSW_OVERFLOW 0x0008 00203 #define FSW_UNDERFLOW 0x0010 00204 #define FSW_PRECISION 0x0020 00205 #define FSW_STACK_FAULT 0x0040 00206 #define FSW_CONDITION_CODE_0 0x0100 00207 #define FSW_CONDITION_CODE_1 0x0200 00208 #define FSW_CONDITION_CODE_2 0x0400 00209 #define FSW_CONDITION_CODE_3 0x4000 00210 00211 #define FSW_ERR_MASK (FSW_INVALID_OPERATION | FSW_DENORMAL | FSW_ZERO_DIVIDE | FSW_OVERFLOW | FSW_UNDERFLOW | FSW_PRECISION | FSW_STACK_FAULT) 00212 00213 00214 #define CPL_STATE(SegCs) (SegCs & RPL_MASK) 00215 00216 // Use the IIPA since that points to the start of the ia32 instruction 00217 #define EIP(frame) ((ULONG) (frame)->StIIPA & 0xffffffff) 00218 #define ESP(frame) ((ULONG) (frame)->IntSp & 0xffffffff) 00219 #define ECX(frame) ((ULONG) (frame)->IntT2 & 0xffffffff) 00220 #define EDX(frame) ((ULONG) (frame)->IntT3 & 0xffffffff) 00221 00222 #define ISRCode(frame) ((USHORT) ((frame)->StISR) & 0xffff) 00223 #define ISRVector(frame) ((UCHAR) ((frame)->StISR >> 16) & 0xff) 00224 00225 #if defined(IADBG) 00226 ULONG IA32Debug = 0x000fffff; 00227 00228 #define IA32_DEBUG_INTERCEPTION 0x00000001 00229 #define IA32_DEBUG_EXCEPTION 0x00000002 00230 #define IA32_DEBUG_INTERRUPT 0x00000004 00231 00232 #define IA32_DEBUG_DIVIDE 0x00000010 00233 #define IA32_DEBUG_DEBUG 0x00000020 00234 #define IA32_DEBUG_OVERFLOW 0x00000040 00235 #define IA32_DEBUG_BOUND 0x00000080 00236 #define IA32_DEBUG_INSTRUCTION 0x00000100 00237 #define IA32_DEBUG_NODEVICE 0x00000200 00238 #define IA32_DEBUG_NOTPRESENT 0x00000400 00239 #define IA32_DEBUG_STACK 0x00000800 00240 #define IA32_DEBUG_GPFAULT 0x00001000 00241 #define IA32_DEBUG_FPFAULT 0x00002000 00242 #define IA32_DEBUG_ALIGNMENT 0x00004000 00243 #define IA32_DEBUG_GATE 0x00008000 00244 #define IA32_DEBUG_BREAK 0x00010000 00245 #define IA32_DEBUG_INTNN 0x00020000 00246 #define IA32_DEBUG_FLAG 0x00040000 00247 #define IA32_DEBUG_LOCK 0x00080000 00248 // 00249 // define debug macro 00250 // 00251 #define IF_IA32TRAP_DEBUG( ComponentFlag ) \ 00252 if (IA32Debug & (IA32_DEBUG_ ## ComponentFlag)) 00253 00254 #else // IADBG 00255 00256 #define IF_IA32TRAP_DEBUG( ComponentFlag ) if (FALSE) 00257 00258 #endif // IADBG