test: eisa.h Source File

00001 /*++ 00002 00003 Copyright (c) 1990 Microsoft Corporation 00004 00005 Module Name: 00006 00007 eisa.h 00008 00009 Abstract: 00010 00011 The module defines the structures, and defines for the EISA chip set. 00012 00013 Author: 00014 00015 Jeff Havens (jhavens) 19-Jun-1991 00016 00017 Revision History: 00018 00019 00020 --*/ 00021 00022 #ifndef _EISA_ 00023 #define _EISA_ 00024 00025 00026 00027 // 00028 // Define the DMA page register structure. 00029 // 00030 00031 typedef struct _DMA_PAGE{ 00032 UCHAR Reserved1; 00033 UCHAR Channel2; 00034 UCHAR Channel3; 00035 UCHAR Channel1; 00036 UCHAR Reserved2[3]; 00037 UCHAR Channel0; 00038 UCHAR Reserved3; 00039 UCHAR Channel6; 00040 UCHAR Channel7; 00041 UCHAR Channel5; 00042 UCHAR Reserved4[3]; 00043 UCHAR RefreshPage; 00044 }DMA_PAGE, *PDMA_PAGE; 00045 00046 // 00047 // Define the DMA stop register structure. 00048 // 00049 00050 typedef struct _DMA_CHANNEL_STOP { 00051 UCHAR ChannelLsb; 00052 UCHAR ChannelMsb; 00053 UCHAR ChannelHsb; 00054 UCHAR Reserved; 00055 }DMA_CHANNEL_STOP, *PDMA_CHANNEL_STOP; 00056 00057 // 00058 // Define DMA 1 address and count structure. 00059 // 00060 00061 typedef struct _DMA1_ADDRESS_COUNT { 00062 UCHAR DmaBaseAddress; 00063 UCHAR DmaBaseCount; 00064 }DMA1_ADDRESS_COUNT, *PDMA1_ADDRESS_COUNT; 00065 00066 // 00067 // Define DMA 2 address and count structure. 00068 // 00069 00070 typedef struct _DMA2_ADDRESS_COUNT { 00071 UCHAR DmaBaseAddress; 00072 UCHAR Reserved1; 00073 UCHAR DmaBaseCount; 00074 UCHAR Reserved2; 00075 }DMA2_ADDRESS_COUNT, *PDMA2_ADDRESS_COUNT; 00076 00077 // 00078 // Define DMA 1 control register structure. 00079 // 00080 00081 typedef struct _DMA1_CONTROL { 00082 DMA1_ADDRESS_COUNT DmaAddressCount[4]; 00083 UCHAR DmaStatus; 00084 UCHAR DmaRequest; 00085 UCHAR SingleMask; 00086 UCHAR Mode; 00087 UCHAR ClearBytePointer; 00088 UCHAR MasterClear; 00089 UCHAR ClearMask; 00090 UCHAR AllMask; 00091 }DMA1_CONTROL, *PDMA1_CONTROL; 00092 00093 // 00094 // Define DMA 2 control register structure. 00095 // 00096 00097 typedef struct _DMA2_CONTROL { 00098 DMA2_ADDRESS_COUNT DmaAddressCount[4]; 00099 UCHAR DmaStatus; 00100 UCHAR Reserved1; 00101 UCHAR DmaRequest; 00102 UCHAR Reserved2; 00103 UCHAR SingleMask; 00104 UCHAR Reserved3; 00105 UCHAR Mode; 00106 UCHAR Reserved4; 00107 UCHAR ClearBytePointer; 00108 UCHAR Reserved5; 00109 UCHAR MasterClear; 00110 UCHAR Reserved6; 00111 UCHAR ClearMask; 00112 UCHAR Reserved7; 00113 UCHAR AllMask; 00114 UCHAR Reserved8; 00115 }DMA2_CONTROL, *PDMA2_CONTROL; 00116 00117 // 00118 // Define Timer control register structure. 00119 // 00120 00121 typedef struct _TIMER_CONTROL { 00122 UCHAR BcdMode : 1; 00123 UCHAR Mode : 3; 00124 UCHAR SelectByte : 2; 00125 UCHAR SelectCounter : 2; 00126 }TIMER_CONTROL, *PTIMER_CONTROL; 00127 00128 // 00129 // Define Timer status register structure. 00130 // 00131 00132 typedef struct _TIMER_STATUS { 00133 UCHAR BcdMode : 1; 00134 UCHAR Mode : 3; 00135 UCHAR SelectByte : 2; 00136 UCHAR CrContentsMoved : 1; 00137 UCHAR OutPin : 1; 00138 }TIMER_STATUS, *PTIMER_STATUS; 00139 00140 // 00141 // Define Mode values. 00142 // 00143 00144 #define TM_SIGNAL_END_OF_COUNT 0 00145 #define TM_ONE_SHOT 1 00146 #define TM_RATE_GENERATOR 2 00147 #define TM_SQUARE_WAVE 3 00148 #define TM_SOFTWARE_STROBE 4 00149 #define TM_HARDWARE_STROBE 5 00150 00151 // 00152 // Define SelectByte values 00153 // 00154 00155 #define SB_COUNTER_LATCH 0 00156 #define SB_LSB_BYTE 1 00157 #define SB_MSB_BYTE 2 00158 #define SB_LSB_THEN_MSB 3 00159 00160 // 00161 // Define SelectCounter values. 00162 // 00163 00164 #define SELECT_COUNTER_0 0 00165 #define SELECT_COUNTER_1 1 00166 #define SELECT_COUNTER_2 2 00167 #define SELECT_READ_BACK 3 00168 00169 // 00170 // Define Timer clock for speaker. 00171 // 00172 00173 #define TIMER_CLOCK_IN 1193167 // 1.193Mhz 00174 00175 // 00176 // Define NMI Status/Control register structure. 00177 // 00178 00179 typedef struct _NMI_STATUS { 00180 UCHAR SpeakerGate : 1; 00181 UCHAR SpeakerData : 1; 00182 UCHAR DisableEisaParity : 1; 00183 UCHAR DisableNmi : 1; 00184 UCHAR RefreshToggle : 1; 00185 UCHAR SpeakerTimer : 1; 00186 UCHAR IochkNmi : 1; 00187 UCHAR ParityNmi : 1; 00188 }NMI_STATUS, *PNMI_STATUS; 00189 00190 // 00191 // Define NMI Enable register structure. 00192 // 00193 00194 typedef struct _NMI_ENABLE { 00195 UCHAR RtClockAddress : 7; 00196 UCHAR NmiDisable : 1; 00197 }NMI_ENABLE, *PNMI_ENABLE; 00198 // 00199 // Define the NMI extended status and control register structure. 00200 // 00201 00202 typedef struct _NMI_EXTENDED_CONTROL { 00203 UCHAR BusReset : 1; 00204 UCHAR EnableNmiPort : 1; 00205 UCHAR EnableFailSafeNmi : 1; 00206 UCHAR EnableBusMasterTimeout : 1; 00207 UCHAR Reserved1 : 1; 00208 UCHAR PendingPortNmi : 1; 00209 UCHAR PendingBusMasterTimeout : 1; 00210 UCHAR PendingFailSafeNmi : 1; 00211 }NMI_EXTENDED_CONTROL, *PNMI_EXTENDED_CONTROL; 00212 00213 // 00214 // Define 82357 register structure. 00215 // 00216 00217 typedef struct _EISA_CONTROL { 00218 DMA1_CONTROL Dma1BasePort; // Offset 0x000 00219 UCHAR Reserved0[16]; 00220 UCHAR Interrupt1ControlPort0; // Offset 0x020 00221 UCHAR Interrupt1ControlPort1; // Offset 0x021 00222 UCHAR Reserved1[32 - 2]; 00223 UCHAR Timer1; // Offset 0x40 00224 UCHAR RefreshRequest; // Offset 0x41 00225 UCHAR SpeakerTone; // Offset 0x42 00226 UCHAR CommandMode1; // Offset 0x43 00227 UCHAR Reserved17[4]; 00228 UCHAR Timer2; // Offset 0x48 00229 UCHAR Reserved13; 00230 UCHAR CpuSpeedControl; // Offset 0x4a 00231 UCHAR CommandMode2; // Offset 0x4b 00232 UCHAR Reserved14[21]; 00233 UCHAR NmiStatus; // Offset 0x61 00234 UCHAR Reserved15[14]; 00235 UCHAR NmiEnable; // Offset 0x70 00236 UCHAR Reserved16[15]; 00237 DMA_PAGE DmaPageLowPort; // Offset 0x080 00238 UCHAR Reserved2[16]; 00239 UCHAR Interrupt2ControlPort0; // Offset 0x0a0 00240 UCHAR Interrupt2ControlPort1; // Offset 0x0a1 00241 UCHAR Reserved3[32-2]; 00242 DMA2_CONTROL Dma2BasePort; // Offset 0x0c0 00243 UCHAR Reserved4[0x320]; 00244 UCHAR Dma1CountHigh[8]; // Offset 0x400 00245 UCHAR Reserved5[2]; 00246 UCHAR Dma1ChainingInterrupt; // Offset 0x40a 00247 UCHAR Dma1ExtendedModePort; // Offset 0x40b 00248 UCHAR MasterControlPort; // Offset 0x40c 00249 UCHAR SteppingLevelRegister; // Offset 0x40d 00250 UCHAR IspTest1; // Offset 0x40e 00251 UCHAR IspTest2; // Offset 0x40f 00252 UCHAR Reserved6[81]; 00253 UCHAR ExtendedNmiResetControl; // Offset 0x461 00254 UCHAR NmiIoInterruptPort; // Offset 0x462 00255 UCHAR Reserved7; 00256 UCHAR LastMaster; // Offset 0x464 00257 UCHAR Reserved8[27]; 00258 DMA_PAGE DmaPageHighPort; // Offset 0x480 00259 UCHAR Reserved12[48]; 00260 UCHAR Dma2HighCount[16]; // Offset 0x4c0 00261 UCHAR Interrupt1EdgeLevel; // Offset 0x4d0 00262 UCHAR Interrupt2EdgeLevel; // Offset 0x4d1 00263 UCHAR Reserved9[2]; 00264 UCHAR Dma2ChainingInterrupt; // Offset 0x4d4 00265 UCHAR Reserved10; 00266 UCHAR Dma2ExtendedModePort; // Offset 0x4d6 00267 UCHAR Reserved11[9]; 00268 DMA_CHANNEL_STOP DmaChannelStop[8]; // Offset 0x4e0 00269 } EISA_CONTROL, *PEISA_CONTROL; 00270 00271 // 00272 // Define initialization command word 1 structure. 00273 // 00274 00275 typedef struct _INITIALIZATION_COMMAND_1 { 00276 UCHAR Icw4Needed : 1; 00277 UCHAR CascadeMode : 1; 00278 UCHAR Unused1 : 2; 00279 UCHAR InitializationFlag : 1; 00280 UCHAR Unused2 : 3; 00281 }INITIALIZATION_COMMAND_1, *PINITIALIZATION_COMMAND_1; 00282 00283 // 00284 // Define initialization command word 4 structure. 00285 // 00286 00287 typedef struct _INITIALIZATION_COMMAND_4 { 00288 UCHAR I80x86Mode : 1; 00289 UCHAR AutoEndOfInterruptMode : 1; 00290 UCHAR Unused1 : 2; 00291 UCHAR SpecialFullyNested : 1; 00292 UCHAR Unused2 : 3; 00293 }INITIALIZATION_COMMAND_4, *PINITIALIZATION_COMMAND_4; 00294 00295 // 00296 // Define EISA interrupt controller operational command values. 00297 // Define operation control word 2 commands. 00298 // 00299 00300 #define NONSPECIFIC_END_OF_INTERRUPT 0x20 00301 #define SPECIFIC_END_OF_INTERRUPT 0x60 00302 00303 // 00304 // Define the IRQL which the slave intterrupts the master controller. 00305 // 00306 00307 #define SLAVE_IRQL_LEVEL 2 00308 00309 // 00310 // Define external EISA interupts 00311 // 00312 00313 #define EISA_EXTERNAL_INTERRUPTS_1 0xf8 00314 #define EISA_EXTERNAL_INTERRUPTS_2 0xbe 00315 00316 // 00317 // Define the DMA mode register structure. 00318 // 00319 00320 typedef struct _DMA_EISA_MODE { 00321 UCHAR Channel : 2; 00322 UCHAR TransferType : 2; 00323 UCHAR AutoInitialize : 1; 00324 UCHAR AddressDecrement : 1; 00325 UCHAR RequestMode : 2; 00326 }DMA_EISA_MODE, *PDMA_EISA_MODE; 00327 00328 // 00329 // Define TransferType values. 00330 // 00331 00332 #define VERIFY_TRANSFER 0x00 00333 #define READ_TRANSFER 0x01 // Read from the device. 00334 #define WRITE_TRANSFER 0x02 // Write to the device. 00335 00336 // 00337 // Define RequestMode values. 00338 // 00339 00340 #define DEMAND_REQUEST_MODE 0x00 00341 #define SINGLE_REQUEST_MODE 0x01 00342 #define BLOCK_REQUEST_MODE 0x02 00343 #define CASCADE_REQUEST_MODE 0x03 00344 00345 // 00346 // Define the DMA extended mode register structure. 00347 // 00348 00349 typedef struct _DMA_EXTENDED_MODE { 00350 UCHAR ChannelNumber : 2; 00351 UCHAR TransferSize : 2; 00352 UCHAR TimingMode : 2; 00353 UCHAR EndOfPacketInput : 1; 00354 UCHAR StopRegisterEnabled : 1; 00355 }DMA_EXTENDED_MODE, *PDMA_EXTENDED_MODE; 00356 00357 // 00358 // Define the DMA extended mode register transfer size values. 00359 // 00360 00361 #define BY_BYTE_8_BITS 0 00362 #define BY_WORD_16_BITS 1 00363 #define BY_BYTE_32_BITS 2 00364 #define BY_BYTE_16_BITS 3 00365 00366 // 00367 // Define the DMA extended mode timing mode values. 00368 // 00369 00370 #define COMPATIBLITY_TIMING 0 00371 #define TYPE_A_TIMING 1 00372 #define TYPE_B_TIMING 2 00373 #define BURST_TIMING 3 00374 00375 #ifndef DMA1_COMMAND_STATUS 00376 00377 00378 // 00379 // Define constants used by Intel 8237A DMA chip 00380 // 00381 00382 #define DMA_SETMASK 4 00383 #define DMA_CLEARMASK 0 00384 #define DMA_READ 4 // These two appear backwards, but I think 00385 #define DMA_WRITE 8 // the DMA docs have them mixed up 00386 #define DMA_SINGLE_TRANSFER 0x40 00387 #define DMA_AUTO_INIT 0x10 // Auto initialization mode 00388 #endif 00389 #endif 00390