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Classes | |
struct | _IETEntry_21064 |
struct | _COUNTERS_21064 |
union | _ABOX_CTL_21064 |
union | _MMCSR_21064 |
union | _DC_STAT_21064 |
struct | _MEMC_CSRS_21066 |
struct | _IOC_CSRS_21066 |
union | _BCR_21066 |
union | _BMR_21066 |
union | _GTR_21066 |
union | _ESR_21066 |
union | _EAR_21066 |
union | _CAR_21066 |
union | _IOC_STAT0_21066 |
union | _IOC_STAT1_21066 |
struct | _PROCESSOR_STATE_21066 |
struct | _LOGOUT_FRAME_21066 |
struct | _CORRECTABLE_FRAME_21066 |
Defines | |
#define | PROCESSOR_BUS_21064 21064 |
#define | ITB_ENTRIES_21064 12 |
#define | DTB_ENTRIES_21064 32 |
#define | PAL_TEMPS_21064 32 |
#define | IRQLMASK_HDW_SUBTABLE_21064 (8) |
#define | IRQLMASK_HDW_SUBTABLE_21064_ENTRIES (64) |
#define | IRQLMASK_SFW_SUBTABLE_21064 (0) |
#define | IRQLMASK_SFW_SUBTABLE_21064_ENTRIES (4) |
#define | IRQLMASK_PC_SUBTABLE_21064 (4) |
#define | IRQLMASK_PC_SUBTABLE_21064_ENTRIES (4) |
#define | PTE_FOR_21064_SHIFT 3 |
#define | PTE_FOW_21064_SHIFT 4 |
#define | PTE_KWE_21064_SHIFT 5 |
#define | PTE_EWE_21064_SHIFT 6 |
#define | PTE_SWE_21064_SHIFT 7 |
#define | PTE_UWE_21064_SHIFT 8 |
#define | PTE_KRE_21064_SHIFT 9 |
#define | PTE_ERE_21064_SHIFT 10 |
#define | PTE_SRE_21064_SHIFT 11 |
#define | PTE_URE_21064_SHIFT 12 |
#define | PTE_PFN_21064_SHIFT 13 |
#define | PTE_PFN_21064_SHIFTMASK 0x1FFFF |
#define | PTE_ASM_21064_SHIFT 34 |
#define | PTE_ALL_21064(itbpte) (itbpte) |
#define | PTE_FOR_21064(itbpte) ( (itbpte.LowPart >> PTE_FOR_21064_SHIFT) & 1) |
#define | PTE_FOW_21064(itbpte) ( (itbpte.LowPart >> PTE_FOW_21064_SHIFT) & 1) |
#define | PTE_KWE_21064(itbpte) ( (itbpte.LowPart >> PTE_KWE_21064_SHIFT) & 1) |
#define | PTE_EWE_21064(itbpte) ( (itbpte.LowPart >> PTE_EWE_21064_SHIFT) & 1) |
#define | PTE_SWE_21064(itbpte) ( (itbpte.LowPart >> PTE_SWE_21064_SHIFT) & 1) |
#define | PTE_UWE_21064(itbpte) ( (itbpte.LowPart >> PTE_UWE_21064_SHIFT) & 1) |
#define | PTE_KRE_21064(itbpte) ( (itbpte.LowPart >> PTE_KRE_21064_SHIFT) & 1) |
#define | PTE_ERE_21064(itbpte) ( (itbpte.LowPart >> PTE_ERE_21064_SHIFT) & 1) |
#define | PTE_SRE_21064(itbpte) ( (itbpte.LowPart >> PTE_SRE_21064_SHIFT) & 1) |
#define | PTE_URE_21064(itbpte) ( (itbpte.LowPart >> PTE_URE_21064_SHIFT) & 1) |
#define | PTE_ASM_21064(itbpte) ( (itbpte.LowPart >> PTE_ASM_21064_SHIFT) & 1) |
#define | PTE_PFN_21064(itbpte) ( (itbpte.LowPart >> PTE_PFN_21064_SHIFT) & PTE_PFN_21064_SHIFTMASK) |
#define | ICCSR_PC0_21064_SHIFT 1 |
#define | ICCSR_PC1_21064_SHIFT 2 |
#define | ICCSR_PCMUX0_21064_SHIFT 9 |
#define | ICCSR_PCMUX0_21064_SHIFTMASK 0xF |
#define | ICCSR_PCMUX1_21064_SHIFT 13 |
#define | ICCSR_PCMUX1_21064_SHIFTMASK 0x7 |
#define | ICCSR_PIPE_21064_SHIFT 16 |
#define | ICCSR_BPE_21064_SHIFT 17 |
#define | ICCSR_JSE_21064_SHIFT 18 |
#define | ICCSR_BHE_21064_SHIFT 19 |
#define | ICCSR_DI_21064_SHIFT 20 |
#define | ICCSR_HWE_21064_SHIFT 21 |
#define | ICCSR_MAP_21064_SHIFT 22 |
#define | ICCSR_FPE_21064_SHIFT 23 |
#define | ICCSR_ASN_21064_SHIFT 28 |
#define | ICCSR_ASN_21064_SHIFTMASK 0x3F |
#define | ICCSR_ALL_21064(iccsr) (iccsr) |
#define | ICCSR_PC0_21064(iccsr) ( (iccsr.LowPart >> ICCSR_PC0_21064_SHIFT) & 1) |
#define | ICCSR_PC1_21064(iccsr) ( (iccsr.LowPart >> ICCSR_PC1_21064_SHIFT) & 1) |
#define | ICCSR_PCMUX0_21064(iccsr) ( (iccsr.LowPart >> ICCSR_PCMUX0_21064_SHIFT) & ICCSR_PCMUX0_21064_SHIFTMASK) |
#define | ICCSR_PCMUX1_21064(iccsr) ( (iccsr.LowPart >> ICCSR_PCMUX1_21064_SHIFT) & ICCSR_PCMUX1_21064_SHIFTMASK) |
#define | ICCSR_PIPE_21064(iccsr) ( (iccsr.LowPart >> ICCSR_PIPE_21064_SHIFT) & 1) |
#define | ICCSR_BPE_21064(iccsr) ( (iccsr.LowPart >> ICCSR_BPE_21064_SHIFT) & 1) |
#define | ICCSR_JSE_21064(iccsr) ( (iccsr.LowPart >> ICCSR_JSE_21064_SHIFT) & 1) |
#define | ICCSR_BHE_21064(iccsr) ( (iccsr.LowPart >> ICCSR_BHE_21064_SHIFT) & 1) |
#define | ICCSR_DI_21064(iccsr) ( (iccsr.LowPart >> ICCSR_DI_21064_SHIFT) & 1) |
#define | ICCSR_HWE_21064(iccsr) ( (iccsr.LowPart >> ICCSR_HWE_21064_SHIFT) & 1) |
#define | ICCSR_MAP_21064(iccsr) ( (iccsr.LowPart >> ICCSR_MAP_21064_SHIFT) & 1) |
#define | ICCSR_FPE_21064(iccsr) ( (iccsr.LowPart >> ICCSR_FPE_21064_SHIFT) & 1) |
#define | ICCSR_ASN_21064(iccsr) (ULONG)( (iccsr.LowPart >> ICCSR_ASN_21064_SHIFT) & ICCSR_ASN_21064_SHIFTMASK) |
#define | PS_CM0_21064_SHIFT 1 |
#define | PS_CM1_21064_SHIFT 34 |
#define | PS_ALL_21064(ps) (ps) |
#define | PS_CM_21064(ps) |
#define | EXCSUM_SWC_21064_SHIFT 2 |
#define | EXCSUM_INV_21064_SHIFT 3 |
#define | EXCSUM_DZE_21064_SHIFT 4 |
#define | EXCSUM_FOV_21064_SHIFT 5 |
#define | EXCSUM_UNF_21064_SHIFT 6 |
#define | EXCSUM_INE_21064_SHIFT 7 |
#define | EXCSUM_IOV_21064_SHIFT 8 |
#define | EXCSUM_MSK_21064_SHIFT 33 |
#define | EXCSUM_ALL_21064(excsum) (excsum) |
#define | EXCSUM_SWC_21064(excsum) ((excsum.LowPart >> EXCSUM_SWC_21064_SHIFT) & 0x1) |
#define | EXCSUM_INV_21064(excsum) ( (excsum.LowPart >> EXCSUM_INV_21064_SHIFT) & 0x1) |
#define | EXCSUM_DZE_21064(excsum) ( (excsum.LowPart >> EXCSUM_DZE_21064_SHIFT) & 0x1) |
#define | EXCSUM_FOV_21064(excsum) ( (excsum.LowPart >> EXCSUM_FOV_21064_SHIFT) & 0x1) |
#define | EXCSUM_UNF_21064(excsum) ( (excsum.LowPart >> EXCSUM_UNF_21064_SHIFT) & 0x1) |
#define | EXCSUM_INE_21064(excsum) ( (excsum.LowPart >> EXCSUM_INE_21064_SHIFT) & 0x1) |
#define | EXCSUM_IOV_21064(excsum) ( (excsum.LowPart >> EXCSUM_IOV_21064_SHIFT) & 0x1) |
#define | EXCSUM_MSK_21064(excsum) ( (excsum.LowPart >> EXCSUM_MSK_21064_SHIFT) & 0x1) |
#define | IRR_HWR_21064_SHIFT 1 |
#define | IRR_SWR_21064_SHIFT 2 |
#define | IRR_ATR_21064_SHIFT 3 |
#define | IRR_CRR_21064_SHIFT 4 |
#define | IRR_HIRR53_21064_SHIFT 5 |
#define | IRR_HIRR53_21064_SHIFTMASK 0x7 |
#define | IRR_PC1_21064_SHIFT 8 |
#define | IRR_PC0_21064_SHIFT 9 |
#define | IRR_HIRR20_21064_SHIFT 10 |
#define | IRR_HIRR20_21064_SHIFTMASK 0x7 |
#define | IRR_SLR_21064_SHIFT 13 |
#define | IRR_SIRR_21064_SHIFT 14 |
#define | IRR_SIRR_21064_SHIFTMASK 0x7FFF |
#define | IRR_ASTRR_21064_SHIFT 29 |
#define | IRR_ASTRR_21064_SHIFTMASK 0xF |
#define | IRR_ALL_21064(irr) (irr) |
#define | IRR_HWR_21064(irr) ( (irr.LowPart >> IRR_HWR_21064_SHIFT) & 0x1) |
#define | IRR_SWR_21064(irr) ( (irr.LowPart >> IRR_SWR_21064_SHIFT) & 0x1) |
#define | IRR_ATR_21064(irr) ( (irr.LowPart >> IRR_ATR_21064_SHIFT) & 0x1) |
#define | IRR_CRR_21064(irr) ( (irr.LowPart >> IRR_CRR_21064_SHIFT) & 0x1) |
#define | IRR_HIRR_21064(irr) |
#define | IRR_PC1_21064(irr) ( (irr.LowPart >> IRR_PC1_21064_SHIFT) & 0x1) |
#define | IRR_PC0_21064(irr) ( (irr.LowPart >> IRR_PC0_21064_SHIFT) & 0x1) |
#define | IRR_SLR_21064(irr) ( (irr.LowPart >> IRR_SLR_21064_SHIFT) & 0x1) |
#define | IRR_SIRR_21064(irr) ( (irr.LowPart >> IRR_SIRR_21064_SHIFT) & IRR_SIRR_21064_SHIFTMASK) |
#define | IRR_ASTRR_21064(irr) ( (irr.LowPart >> IRR_ASTRR_21064_SHIFT) & IRR_ASTRR_21064_SHIFTMASK) |
#define | IER_CRR_21064_SHIFT 4 |
#define | IER_HIER53_21064_SHIFT 5 |
#define | IER_HIER53_21064_SHIFTMASK 0x7 |
#define | IER_PC1_21064_SHIFT 8 |
#define | IER_PC0_21064_SHIFT 9 |
#define | IER_HIER20_21064_SHIFT 10 |
#define | IER_HIER20_21064_SHIFTMASK 0x7 |
#define | IER_SLR_21064_SHIFT 13 |
#define | IER_SIER_21064_SHIFT 14 |
#define | IER_SIER_21064_SHIFTMASK 0x7FFF |
#define | IER_ASTER_21064_SHIFT 29 |
#define | IER_ASTER_21064_SHIFTMASK 0xF |
#define | IER_ALL_21064(ier) (ier) |
#define | IER_CRR_21064(ier) ( (ier.LowPart >> IER_CRR_21064_SHIFT) & 0x1) |
#define | IER_HIER_21064(ier) |
#define | IER_PC1_21064(ier) ( (ier.LowPart >> IER_PC1_21064_SHIFT) & 0x1) |
#define | IER_PC0_21064(ier) ( (ier.LowPart >> IER_PC0_21064_SHIFT) & 0x1) |
#define | IER_SLR_21064(ier) ( (ier.LowPart >> IER_SLR_21064_SHIFT) & 0x1) |
#define | IER_SIER_21064(ier) ( (ier.LowPart >> IER_SIER_21064_SHIFT) & IER_SIER_21064_SHIFTMASK) |
#define | IER_ASTER_21064(ier) ( (ier.LowPart >> IER_ASTER_21064_SHIFT) & IER_ASTER_21064_SHIFTMASK) |
#define | ABOXCTL_ALL_21064(aboxctl) ((aboxctl).all) |
#define | ABOXCTL_WBDIS_21064(aboxctl) ((aboxctl).bits.wb_dis) |
#define | ABOXCTL_MCHKEN_21064(aboxctl) ((aboxctl).bits.mchk_en) |
#define | ABOXCTL_CRDEN_21064(aboxctl) ((aboxctl).bits.crd_en) |
#define | ABOXCTL_ICSBUFEN_21064(aboxctl) ((aboxctl).bits.ic_sbuf_en) |
#define | ABOXCTL_SPE1_21064(aboxctl) ((aboxctl).bits.spe_1) |
#define | ABOXCTL_SPE2_21064(aboxctl) ((aboxctl).bits.spe_2) |
#define | ABOXCTL_EMDEN_21064(aboxctl) ((aboxctl).bits.emd_en) |
#define | ABOXCTL_DCENA_21064(aboxctl) ((aboxctl).bits.dc_ena) |
#define | ABOXCTL_DCFHIT_21064(aboxctl) ((aboxctl).bits.dc_fhit) |
#define | MMCSR_ALL_21064(mmcsr) ((mmcsr).all) |
#define | MMCSR_WR_21064(mmcsr) ((mmcsr).bits.Wr) |
#define | MMCSR_ACV_21064(mmcsr) ((mmcsr).bits.Acv) |
#define | MMCSR_FOR_21064(mmcsr) ((mmcsr).bits.For) |
#define | MMCSR_FOW_21064(mmcsr) ((mmcsr).bits.Fow) |
#define | MMCSR_RA_21064(mmcsr) ((mmcsr).bits.Ra) |
#define | MMCSR_OPCODE_21064(mmcsr) ((mmcsr).bits.Opcode) |
#define | DCSTAT_ALL_21064(dcstat) ((dcstat).all) |
#define | DCSTAT_DCHIT_21064(dcstat) ((dcstat).bits.DcHit) |
#define | DCSTAT_DCPARITY_ERROR_21064(dcstat) ((dcstat).bits.DCacheParityError) |
#define | DCSTAT_ICPARITY_ERROR_21064(dcstat) ((dcstat).bits.ICacheParityError) |
#define | MEMORY_BANKS_21066 (4) |
CORE_21064. | |
#define | MEMORY_CONTROLLER_PHYSICAL_21066 (0x120000000) |
#define | IO_CONTROLLER_PHYSICAL_21066 (0x180000000) |
#define | LCA_PHYSICAL_ADDRESS_BITS 34 |
#define | LCA_VIRTUAL_ADDRESS_BITS 43 |
Typedefs | |
typedef _IETEntry_21064 | IETEntry_21064 |
typedef _IETEntry_21064 * | PIETEntry_21064 |
typedef _COUNTERS_21064 | COUNTERS_21064 |
typedef _COUNTERS_21064 * | PCOUNTERS_21064 |
typedef enum _AXP21064_PCCOUNTER | AXP21064_PCCOUNTER |
typedef enum _AXP21064_PCCOUNTER * | PAXP21064_PCCOUNTER |
typedef enum _AXP21064_PCMUXCONTROL | AXP21064_PCMUXCONTROL |
typedef enum _AXP21064_PCMUXCONTROL * | PAXP21064_PCMUXCONTROL |
typedef enum _AXP21064_PCEVENTCOUNT | AXP21064_PCEVENTCOUNT |
typedef enum _AXP21064_PCEVENTCOUNT * | PAXP21064_PCEVENTCOUNT |
typedef enum _AXP21064_EVENTCOUNT | AXP21064_EVENTCOUNT |
typedef enum _AXP21064_EVENTCOUNT * | PAXP21064_EVENTCOUNT |
typedef LARGE_INTEGER | ITB_PTE_21064 |
typedef ITB_PTE_21064 * | PITB_PTE_21064 |
typedef LARGE_INTEGER | DTB_PTE_21064 |
typedef DTB_PTE_21064 * | PDTB_PTE_21064 |
typedef LARGE_INTEGER | ICCSR_21064 |
typedef ICCSR_21064 * | PICCSR_21064 |
typedef LARGE_INTEGER | PS_21064 |
typedef PS_21064 * | PPS_21064 |
typedef LARGE_INTEGER | EXC_SUM_21064 |
typedef EXC_SUM_21064 * | PEXC_SUM_21064 |
typedef LARGE_INTEGER | IRR_21064 |
typedef IRR_21064 * | PIRR_21064 |
typedef LARGE_INTEGER | IER_21064 |
typedef IER_21064 * | PIER_21064 |
typedef _ABOX_CTL_21064 | ABOX_CTL_21064 |
typedef _ABOX_CTL_21064 * | PABOX_CTL_21064 |
typedef _MMCSR_21064 | MMCSR_21064 |
typedef _MMCSR_21064 * | PMMCSR_21064 |
typedef _DC_STAT_21064 | DC_STAT_21064 |
typedef _DC_STAT_21064 * | PDC_STAT_21064 |
typedef _MEMC_CSRS_21066 | MEMC_CSRS_21066 |
typedef _MEMC_CSRS_21066 * | PMEMC_CSRS_21066 |
typedef _IOC_CSRS_21066 | IOC_CSRS_21066 |
typedef _IOC_CSRS_21066 * | PIOC_CSRS_21066 |
typedef _BCR_21066 | BCR_21066 |
typedef _BCR_21066 * | PBCR_21066 |
typedef _BMR_21066 | BMR_21066 |
typedef _BMR_21066 * | PBMR_21066 |
typedef _GTR_21066 | GTR_21066 |
typedef _GTR_21066 * | PGTR_21066 |
typedef _ESR_21066 | ESR_21066 |
typedef _ESR_21066 * | PESR_21066 |
typedef _EAR_21066 | EAR_21066 |
typedef _EAR_21066 * | PEAR_21066 |
typedef _CAR_21066 | CAR_21066 |
typedef _CAR_21066 * | PCAR_21066 |
typedef _IOC_STAT0_21066 | IOC_STAT0_21066 |
typedef _IOC_STAT0_21066 * | PIOC_STAT0_21066 |
typedef _IOC_STAT1_21066 | IOC_STAT1_21066 |
typedef _IOC_STAT1_21066 * | PIOC_STAT1_21066 |
typedef _PROCESSOR_STATE_21066 | PROCESSOR_STATE_21066 |
typedef _PROCESSOR_STATE_21066 * | PPROCESSOR_STATE_21066 |
typedef _LOGOUT_FRAME_21066 | LOGOUT_FRAME_21066 |
typedef _LOGOUT_FRAME_21066 * | PLOGOUT_FRAME_21066 |
typedef _CORRECTABLE_FRAME_21066 | CORRECTABLE_FRAME_21066 |
Enumerations | |
enum | _AXP21064_PCCOUNTER { Ev4PerformanceCounter0 = 0, Ev4PerformanceCounter1 = 1 } |
enum | _AXP21064_PCMUXCONTROL { Ev4TotalIssues = 0x0, Ev4PipelineDry = 0x2, Ev4LoadInstruction = 0x4, Ev4PipelineFrozen = 0x6, Ev4BranchInstructions = 0x8, Ev4PalMode = 0xb, Ev4TotalCycles = 0xa, Ev4TotalNonIssues = 0xc, Ev4ExternalCounter0 = 0xe, Ev4DcacheMiss = 0x0, Ev4IcacheMiss = 0x1, Ev4DualIssues = 0x2, Ev4BranchMispredicts = 0x3, Ev4FPInstructions = 0x4, Ev4IntegerOperate = 0x5, Ev4StoreInstructions = 0x6, Ev4ExternalCounter1 = 0x7 } |
enum | _AXP21064_PCEVENTCOUNT { Ev4CountEvents2xx8 = 0x100, Ev4CountEvents2xx12 = 0x1000, Ev4CountEvents2xx16 = 0x10000 } |
enum | _AXP21064_EVENTCOUNT { Ev4EventCountHigh = 1, Ev4EventCountLow = 0 } |
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