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Classes |
| struct | _DMA_REGISTER |
| struct | _DMA_LARGE_REGISTER |
| struct | _DMA_CHANNEL |
| struct | _DMA_REGISTERS |
| struct | _DMA_CHANNEL_MODE |
| struct | _DMA_CHANNEL_ENABLE |
| struct | _TRANSLATION_ENTRY |
Defines |
| #define | LOAD_CLEAN_EXCLUSIVE 0x20 |
| #define | DISABLE_EISA_MEMORY 0x10 |
| #define | ENABLE_PROCESSOR_B 0x08 |
| #define | MAP_PROM 0x04 |
| #define | ENABLE_CHANNEL_INTERRUPTS (1 << 0) |
| #define | ENABLE_DEVICE_INTERRUPTS (1 << 1) |
| #define | ENABLE_EISA_INTERRUPTS (1 << 2) |
| #define | ENABLE_TIMER_INTERRUPTS (1 << 3) |
| #define | ENABLE_IP_INTERRUPTS (1 << 4) |
| #define | EISA_NMI_VECTOR 0x8000 |
| #define | NMI_SRC_MEMORY_ERROR 1 |
| #define | NMI_SRC_R4000_ADDRESS_ERROR 2 |
| #define | NMI_SRC_IO_CACHE_ERROR 4 |
| #define | NMI_SRC_ADR_NMI 8 |
| #define | ACCESS_40NS 0x0 |
| #define | ACCESS_80NS 0x1 |
| #define | ACCESS_120NS 0x2 |
| #define | ACCESS_160NS 0x3 |
| #define | ACCESS_200NS 0x4 |
| #define | ACCESS_240NS 0x5 |
| #define | ACCESS_280NS 0x6 |
| #define | ACCESS_320NS 0x7 |
| #define | WIDTH_8BITS 0x1 |
| #define | WIDTH_16BITS 0x2 |
| #define | WIDTH_32BITS 0x3 |
| #define | DMA_READ_OP 0x0 |
| #define | DMA_WRITE_OP 0x1 |
| #define | SONIC_ADDRESS_ERROR 4 |
| #define | SONIC_MEMORY_ERROR 0x40 |
| #define | EISA_ADDRESS_ERROR 1 |
| #define | EISA_MEMORY_ERROR 2 |
| #define | LFAR_ADDRESS_MASK 0xfffff000 |
| #define | RFAR_ADDRESS_MASK 0x00ffffc0 |
| #define | MFAR_ADDRESS_MASK 0x1ffffff0 |
| #define | ECC_SINGLE_BIT_DP0 0x02000000 |
| #define | ECC_SINGLE_BIT_DP1 0x20000000 |
| #define | ECC_SINGLE_BIT ( ECC_SINGLE_BIT_DP0 | ECC_SINGLE_BIT_DP1 ) |
| #define | ECC_DOUBLE_BIT_DP0 0x04000000 |
| #define | ECC_DOUBLE_BIT_DP1 0x40000000 |
| #define | ECC_DOUBLE_BIT ( ECC_DOUBLE_BIT_DP0 | ECC_DOUBLE_BIT_DP1 ) |
| #define | ECC_MULTIPLE_BIT_DP0 0x08000000 |
| #define | ECC_MULTIPLE_BIT_DP1 0x80000000 |
| #define | ECC_FORCE_DP0 0x010000 |
| #define | ECC_FORCE_DP1 0x100000 |
| #define | ECC_DISABLE_SINGLE_DP0 0x020000 |
| #define | ECC_DISABLE_SINGLE_DP1 0x200000 |
| #define | ECC_ENABLE_DP0 0x040000 |
| #define | ECC_ENABLE_DP1 0x400000 |
| #define | DIAG_NMI_SWITCH 2 |
| #define | SINGLE_ERROR 1 |
| #define | MULTIPLE_ERROR 2 |
| #define | RFAR_CACHE_FLUSH 4 |
Typedefs |
| typedef _DMA_REGISTER | DMA_REGISTER |
| typedef _DMA_REGISTER * | PDMA_REGISTER |
| typedef _DMA_LARGE_REGISTER | DMA_LARGE_REGISTER |
| typedef _DMA_LARGE_REGISTER * | PDMA_LARGE_REGISTER |
| typedef _DMA_CHANNEL | DMA_CHANNEL |
| typedef _DMA_CHANNEL * | PDMA_CHANNEL |
| typedef _DMA_REGISTERS | DMA_REGISTERS |
| typedef _DMA_REGISTERS * | PDMA_REGISTERS |
| typedef _DMA_CHANNEL_MODE | DMA_CHANNEL_MODE |
| typedef _DMA_CHANNEL_MODE * | PDMA_CHANNEL_MODE |
| typedef _DMA_CHANNEL_ENABLE | DMA_CHANNEL_ENABLE |
| typedef _DMA_CHANNEL_ENABLE * | PDMA_CHANNEL_ENABLE |
| typedef _TRANSLATION_ENTRY | TRANSLATION_ENTRY |
| typedef _TRANSLATION_ENTRY * | PTRANSLATION_ENTRY |
