test: axp21164.h File Reference

00997 { 00998 Ev5Cycles = 0x0, 00999 Ev5Instructions = 0x1, 01000 Ev5NonIssue = 0x0, 01001 Ev5SplitIssue = 0x1, 01002 Ev5PipeDry = 0x2, 01003 Ev5ReplayTrap = 0x3, 01004 Ev5SingleIssue = 0x4, 01005 Ev5DualIssue = 0x5, 01006 Ev5TripleIssue = 0x6, 01007 Ev5QuadIssue = 0x7, 01008 Ev5FlowChangeInst = 0x8, 01009 Ev5IntOpsIssued = 0x9, 01010 Ev5FPOpsIssued = 0xa, 01011 Ev5LoadsIssued = 0xb, 01012 Ev5StoresIssued = 0xc, 01013 Ev5IcacheIssued = 0xd, 01014 Ev5DcacheAccesses = 0xe, 01015 Ev5CBOXInput1 = 0xf, 01016 Ev5LongStalls = 0x0, 01017 Ev5PCMispredicts = 0x2, 01018 Ev5BRMispredicts = 0x3, 01019 Ev5IcacheRFBMisses = 0x4, 01020 Ev5ITBMisses = 0x5, 01021 Ev5DcacheLDMisses = 0x6, 01022 Ev5DTBMisses = 0x7, 01023 Ev5LDMergedMAF = 0x8, 01024 Ev5LDUReplayTraps = 0x9, 01025 Ev5WBMAFReplayTraps = 0xa, 01026 Ev5ExternPerfmonhInput = 0xb, 01027 Ev5CPUCycles = 0xc, 01028 Ev5MBStallCycles = 0xd, 01029 Ev5LDxLInstIssued = 0xe, 01030 Ev5CBOXInput2 = 0xf, 01031 01032 // 01033 // Special MUX controls 01034 // 01035 01036 Ev5PcSpecial = 0x10, 01037 01038 Ev5JsrRetIssued = 0x10, 01039 Ev5CondBrIssued = 0x11, 01040 Ev5AllFlowIssued = 0x12, 01041 01042 Ev5ScMux1 = 0x20, 01043 Ev5ScAccesses = 0x20, 01044 Ev5ScReads = 0x21, 01045 Ev5ScWrites = 0x22, 01046 Ev5ScVictims = 0x23, 01047 Ev5ScUndefined = 0x24, 01048 Ev5ScBcacheAccesses = 0x25, 01049 Ev5ScBcacheVictims = 0x26, 01050 Ev5ScSystemCmdReq = 0x27, 01051 Ev5ScMux2 = 0x28, 01052 Ev5ScMisses = 0x28, 01053 Ev5ScReadMisses = 0x29, 01054 Ev5ScWriteMisses = 0x2a, 01055 Ev5ScSharedWrites = 0x2b, 01056 Ev5ScWrites2 = 0x2c, 01057 Ev5ScBcacheMisses = 0x2d, 01058 Ev5ScSysInvalidate = 0x2e, 01059 Ev5ScSysReadReq = 0x2f, 01060 01061 } AXP21164_PCMUXCONTROL, *PAXP21164_PCMUXCONTROL;

axp21164.h File Reference

Classes

Defines

Typedefs

Enumerations

Define Documentation

Typedef Documentation

Enumeration Type Documentation


Classes
union	_ITB_PTE_21164
union	_ITB_PTE_TEMP_21164
union	_ITB_ASN_21164
union	_ICPERR_STAT_21164
union	_EXC_SUM_21164
union	_PS_21164
union	_ICSR_21164
union	_SIRR_21164
union	_HWINT_CLR_21164
union	_ISR_21164
union	_PMCTR_21164
union	_DTB_ASN_21164
union	_DTB_CM_21164
union	_DTB_PTE_21164
union	_DTB_PTE_TEMP_21164
union	_MM_STAT_21164
union	_DC_PERR_STAT_21164
union	_MCSR_21164
union	_DC_MODE_21164
union	_MAF_MODE_21164
union	_ALT_MODE_21164
union	_CC_CTL_21164
struct	_CBOX_IPRS_21164
union	_SC_CTL_21164
union	_SC_ADDR_21164
union	_SC_STAT_21164
union	_BC_CONTROL_21164
union	_BC_CONFIG_21164
union	_EI_STAT_21164
union	_EI_ADDR_21164
union	_BC_TAG_ADDR_21164
union	_FILL_SYN_21164
struct	_CBOX_IPRS_21164PC
union	_CBOX_CONFIG_21164PC
union	_CBOX_ADDRESS_21164PC
union	_CBOX_STATUS_21164PC
union	_CBOX_CONFIG2_21164PC
union	_IMSK_21164
struct	_COUNTERS_21164
struct	_PROCESSOR_STATE_21164
struct	_LOGOUT_FRAME_21164
struct	_CORRECTABLE_FRAME_21164
Defines
#define	PROCESSOR_BUS_21164 21164
#define	EV5_USER_IO_ADDRESS_SPACE (ULONGLONG)(0x800000000)
#define	EV5_IO_BASE_PHYSICAL 0x8000000000
#define	ITB_ENTRIES_21164 32
#define	DTB_ENTRIES_21164 64
#define	PAL_TEMPS_21164 24
#define	BASE_SUPERVA (ULONGLONG)(0xfffffc0000000000)
#define	SC_CTL_PA (ULONGLONG)(0xfffff000a8)
#define	SC_STAT_PA (ULONGLONG)(0xfffff000e8)
#define	SC_ADDR_PA (ULONGLONG)(0xfffff00188)
#define	BC_CONTROL_PA (ULONGLONG)(0xfffff00128)
#define	BC_CONFIG_PA (ULONGLONG)(0xfffff001c8)
#define	BC_TAG_ADDR_PA (ULONGLONG)(0xfffff00108)
#define	EI_STAT_PA (ULONGLONG)(0xfffff00168)
#define	EI_ADDR_PA (ULONGLONG)(0xfffff00148)
#define	FILL_SYN_PA (ULONGLONG)(0xfffff00068)
#define	LD_LOCK_PA (ULONGLONG)(0xfffff001e8)
#define	SC_CTL_SVA (ULONGLONG)( BASE_SUPERVA \| SC_CTL_PA )
#define	SC_STAT_SVA (ULONGLONG)( BASE_SUPERVA \| SC_STAT_PA )
#define	SC_ADDR_SVA (ULONGLONG)( BASE_SUPERVA \| SC_ADDR_PA )
#define	BC_CONTROL_SVA (ULONGLONG)( BASE_SUPERVA \| BC_CONTROL_PA )
#define	BC_CONFIG_SVA (ULONGLONG)( BASE_SUPERVA \| BC_CONFIG_PA )
#define	BC_TAG_ADDR_SVA (ULONGLONG)( BASE_SUPERVA \| BC_TAG_ADDR_PA )
#define	EI_STAT_SVA (ULONGLONG)( BASE_SUPERVA \| EI_STAT_PA )
#define	EI_ADDR_SVA (ULONGLONG)( BASE_SUPERVA \| EI_ADDR_PA )
#define	FILL_SYN_SVA (ULONGLONG)( BASE_SUPERVA \| FILL_SYN_PA )
#define	LD_LOCK_SVA (ULONGLONG)( BASE_SUPERVA \| LD_LOCK_PA )
#define	CBOX_CONFIG_PA (ULONGLONG)(0xfffff00008)
#define	CBOX_ADDRESS_PA (ULONGLONG)(0xfffff00088)
#define	CBOX_STATUS_PA (ULONGLONG)(0xfffff00108)
#define	CBOX_CONFIG2_PA (ULONGLONG)(0xfffff00188)
#define	CBOX_CONFIG_SVA (ULONGLONG)( BASE_SUPERVA \| CBOX_CONFIG_PA )
#define	CBOX_ADDRESS_SVA (ULONGLONG)( BASE_SUPERVA \| CBOX_ADDRESS_PA )
#define	CBOX_STATUS_SVA (ULONGLONG)( BASE_SUPERVA \| CBOX_STATUS_PA )
#define	CBOX_CONFIG2_SVA (ULONGLONG)( BASE_SUPERVA \| CBOX_CONFIG2_PA )
#define	EV5_IPL0 (0)
#define	EV5_IPL1 (1)
#define	EV5_IPL2 (2)
#define	EV5_IPL3 (3)
#define	EV5_IPL4 (4)
#define	EV5_IPL5 (5)
#define	EV5_IPL6 (6)
#define	EV5_IPL7 (7)
#define	EV5_IPL8 (8)
#define	EV5_IPL9 (9)
#define	EV5_IPL10 (10)
#define	EV5_IPL11 (11)
#define	EV5_IPL12 (12)
#define	EV5_IPL13 (13)
#define	EV5_IPL14 (14)
#define	EV5_IPL15 (15)
#define	EV5_IPL16 (16)
#define	EV5_IPL17 (17)
#define	EV5_IPL18 (18)
#define	EV5_IPL19 (19)
#define	EV5_IPL20 (20)
#define	EV5_IPL21 (21)
#define	EV5_IPL22 (22)
#define	EV5_IPL23 (23)
#define	EV5_IPL24 (24)
#define	EV5_IPL25 (25)
#define	EV5_IPL26 (26)
#define	EV5_IPL27 (27)
#define	EV5_IPL28 (28)
#define	EV5_IPL29 (29)
#define	EV5_IPL30 (30)
#define	EV5_IPL31 (31)
#define	EV5_IPL20_VECTOR (20)
#define	EV5_IPL21_VECTOR (21)
#define	EV5_IPL22_VECTOR (22)
#define	EV5_IPL23_VECTOR (23)
#define	EV5_IRQ0_VECTOR EV5_IPL20_VECTOR
#define	EV5_IRQ1_VECTOR EV5_IPL21_VECTOR
#define	EV5_IRQ2_VECTOR EV5_IPL22_VECTOR
#define	EV5_IRQ3_VECTOR EV5_IPL23_VECTOR
#define	EV5_HALT_VECTOR (14)
#define	EV5_PFL_VECTOR (24)
#define	EV5_MCHK_VECTOR (12)
#define	EV5_CRD_VECTOR (25)
#define	EV5_PC0_VECTOR (6)
#define	EV5_PC1_VECTOR (8)
#define	EV5_PC2_VECTOR (15)
#define	EV5_PHYSICAL_ADDRESS_BITS 40
#define	EV5_VIRTUAL_ADDRESS_BITS 43
Typedefs
typedef _ITB_PTE_21164	ITB_PTE_21164
typedef _ITB_PTE_21164 *	PITB_PTE_21164
typedef _ITB_PTE_TEMP_21164	ITB_PTE_TEMP_21164
typedef _ITB_PTE_TEMP_21164 *	PITB_PTE_TEMP_21164
typedef _ITB_ASN_21164	ITB_ASN_21164
typedef _ITB_ASN_21164 *	PITB_ASN_21164
typedef _ICPERR_STAT_21164	ICPERR_STAT_21164
typedef _ICPERR_STAT_21164 *	PICPERR_STAT_21164
typedef _EXC_SUM_21164	EXC_SUM_21164
typedef _EXC_SUM_21164 *	PEXC_SUM_21164
typedef _PS_21164	PS_21164
typedef _PS_21164 *	PPS_21164
typedef _ICSR_21164	ICSR_21164
typedef _ICSR_21164 *	PICSR_21164
typedef _SIRR_21164	SIRR_21164
typedef _SIRR_21164 *	PSIRR_21164
typedef _HWINT_CLR_21164	HWINT_CLR_21164
typedef _HWINT_CLR_21164 *	PHW_INTCLR_21164
typedef _ISR_21164	ISR_21164
typedef _ISR_21164 *	PISR_21164
typedef _PMCTR_21164	PMCTR_21164
typedef _PMCTR_21164 *	PPMCTR_21164
typedef _DTB_ASN_21164	DTB_ASN_21164
typedef _DTB_ASN_21164 *	PDTB_ASN_21164
typedef _DTB_CM_21164	DTB_CM_21164
typedef _DTB_CM_21164 *	PDTB_CM_21164
typedef _DTB_PTE_21164	DTB_PTE_21164
typedef _DTB_PTE_21164 *	PDTB_PTE_21164
typedef _DTB_PTE_TEMP_21164	DTB_PTE_TEMP_21164
typedef _DTB_PTE_TEMP_21164 *	PDTB_PTE_TEMP_21164
typedef _MM_STAT_21164	MM_STAT_21164
typedef _MM_STAT_21164 *	PMM_STAT_21164
typedef _DC_PERR_STAT_21164	DC_PERR_STAT_21164
typedef _DC_PERR_STAT_21164 *	PDC_PERR_STAT_21164
typedef _MCSR_21164	MCSR_21164
typedef _MCSR_21164 *	PMCSR_21164
typedef _DC_MODE_21164	DC_MODE_21164
typedef _DC_MODE_21164 *	PDC_MODE_21164
typedef _MAF_MODE_21164	MAF_MODE_21164
typedef _MAF_MODE_21164 *	PMAF_MODE_21164
typedef _ALT_MODE_21164	ALT_MODE_21164
typedef _ALT_MODE_21164 *	PALT_MODE_21164
typedef _CC_CTL_21164	CC_CTL_21164
typedef _CC_CTL_21164 *	PCC_CTL_21164
typedef _CBOX_IPRS_21164	CBOX_IPRS_21164
typedef _CBOX_IPRS_21164 *	PCBOX_IPRS_21164
typedef _SC_CTL_21164	SC_CTL_21164
typedef _SC_CTL_21164 *	PSC_CTL_21164
typedef _SC_ADDR_21164	SC_ADDR_21164
typedef _SC_ADDR_21164 *	PSC_ADDR_21164
typedef _SC_STAT_21164	SC_STAT_21164
typedef _SC_STAT_21164 *	PSC_STAT_21164
typedef _BC_CONTROL_21164	BC_CONTROL_21164
typedef _BC_CONTROL_21164 *	PBC_CONTROL_21164
typedef _BC_CONFIG_21164	BC_CONFIG_21164
typedef _BC_CONFIG_21164 *	PBC_CONFIG_21164
typedef _EI_STAT_21164	EI_STAT_21164
typedef _EI_STAT_21164 *	PEI_STAT_21164
typedef _EI_ADDR_21164	EI_ADDR_21164
typedef _EI_ADDR_21164 *	PEI_ADDR_21164
typedef _BC_TAG_ADDR_21164	BC_TAG_ADDR_21164
typedef _BC_TAG_ADDR_21164 *	PBC_TAG_ADDR_21164
typedef _FILL_SYN_21164	FILL_SYN_21164
typedef _FILL_SYN_21164 *	PFILL_SYN_21164
typedef _CBOX_IPRS_21164PC	CBOX_IPRS_21164PC
typedef _CBOX_IPRS_21164PC *	PCBOX_IPRS_21164PC
typedef _CBOX_CONFIG_21164PC	CBOX_CONFIG_21164PC
typedef _CBOX_CONFIG_21164PC *	PCBOX_CONFIG_21164PC
typedef _CBOX_ADDRESS_21164PC	CBOX_ADDRESS_21164PC
typedef _CBOX_ADDRESS_21164PC *	PCBOX_ADDRESS_21164PC
typedef _CBOX_STATUS_21164PC	CBOX_STATUS_21164PC
typedef _CBOX_STATUS_21164PC *	PCBOX_STATUS_21164PC
typedef _CBOX_CONFIG2_21164PC	CBOX_CONFIG2_21164PC
typedef _CBOX_CONFIG2_21164PC *	PCBOX_CONFIG2_21164PC
typedef _IMSK_21164	IMSK_21164
typedef _IMSK_21164 *	PIMSK_21164
typedef _COUNTERS_21164	COUNTERS_21164
typedef _COUNTERS_21164 *	PCOUNTERS_21164
typedef enum _AXP21164_PCCOUNTER	AXP21164_PCCOUNTER
typedef enum _AXP21164_PCCOUNTER *	PAXP21164_PCCOUNTER
typedef enum _AXP21164_PCMUXCONTROL	AXP21164_PCMUXCONTROL
typedef enum _AXP21164_PCMUXCONTROL *	PAXP21164_PCMUXCONTROL
typedef enum _AXP21164_PCEVENTCOUNT	AXP21164_PCEVENTCOUNT
typedef enum _AXP21164_PCEVENTCOUNT *	PAXP21164_PCEVENTCOUNT
typedef enum _COUNTER_CONTROL	COUNTER_CONTROL
typedef enum _COUNTER_CONTROL *	PCOUNTER_CONTROL
typedef _PROCESSOR_STATE_21164	PROCESSOR_STATE_21164
typedef _PROCESSOR_STATE_21164 *	PPROCESSOR_STATE_21164
typedef _LOGOUT_FRAME_21164	LOGOUT_FRAME_21164
typedef _LOGOUT_FRAME_21164 *	PLOGOUT_FRAME_21164
typedef _CORRECTABLE_FRAME_21164	CORRECTABLE_FRAME_21164
Enumerations
enum	_AXP21164_PCCOUNTER { Ev5PerformanceCounter0 = 0, Ev5PerformanceCounter1 = 1, Ev5PerformanceCounter2 = 2 }
enum	_AXP21164_PCMUXCONTROL { Ev5Cycles = 0x0, Ev5Instructions = 0x1, Ev5NonIssue = 0x0, Ev5SplitIssue = 0x1, Ev5PipeDry = 0x2, Ev5ReplayTrap = 0x3, Ev5SingleIssue = 0x4, Ev5DualIssue = 0x5, Ev5TripleIssue = 0x6, Ev5QuadIssue = 0x7, Ev5FlowChangeInst = 0x8, Ev5IntOpsIssued = 0x9, Ev5FPOpsIssued = 0xa, Ev5LoadsIssued = 0xb, Ev5StoresIssued = 0xc, Ev5IcacheIssued = 0xd, Ev5DcacheAccesses = 0xe, Ev5CBOXInput1 = 0xf, Ev5LongStalls = 0x0, Ev5PCMispredicts = 0x2, Ev5BRMispredicts = 0x3, Ev5IcacheRFBMisses = 0x4, Ev5ITBMisses = 0x5, Ev5DcacheLDMisses = 0x6, Ev5DTBMisses = 0x7, Ev5LDMergedMAF = 0x8, Ev5LDUReplayTraps = 0x9, Ev5WBMAFReplayTraps = 0xa, Ev5ExternPerfmonhInput = 0xb, Ev5CPUCycles = 0xc, Ev5MBStallCycles = 0xd, Ev5LDxLInstIssued = 0xe, Ev5CBOXInput2 = 0xf, Ev5PcSpecial = 0x10, Ev5JsrRetIssued = 0x10, Ev5CondBrIssued = 0x11, Ev5AllFlowIssued = 0x12, Ev5ScMux1 = 0x20, Ev5ScAccesses = 0x20, Ev5ScReads = 0x21, Ev5ScWrites = 0x22, Ev5ScVictims = 0x23, Ev5ScUndefined = 0x24, Ev5ScBcacheAccesses = 0x25, Ev5ScBcacheVictims = 0x26, Ev5ScSystemCmdReq = 0x27, Ev5ScMux2 = 0x28, Ev5ScMisses = 0x28, Ev5ScReadMisses = 0x29, Ev5ScWriteMisses = 0x2a, Ev5ScSharedWrites = 0x2b, Ev5ScWrites2 = 0x2c, Ev5ScBcacheMisses = 0x2d, Ev5ScSysInvalidate = 0x2e, Ev5ScSysReadReq = 0x2f }
enum	_AXP21164_PCEVENTCOUNT { Ev5CountEvents2xx8 = 0x100, Ev5CountEvents2xx14 = 0x4000, Ev5CountEvents2xx16 = 0x10000 }
enum	_COUNTER_CONTROL { Ev5CounterDisable = 0x0, Ev5InterruptDisable = 0x1, Ev5EventCountLow = 0x2, Ev5EventCountHigh = 0x3 }