test: axp21264.h Source File

00001 /*++ BUILD Version: 0000 Increment this if a change has global effects 00002 00003 Copyright (c) 1996 Digital Euipment Corporation 00004 00005 Module Name: 00006 00007 axp21264.h 00008 00009 Abstract: 00010 00011 This module defines the DECchip 21264-specific structures that are 00012 defined in the PAL but must be visible to the HAL. 00013 00014 Revision History: 00015 00016 --*/ 00017 00018 #ifndef _AXP21264_ 00019 #define _AXP21264_ 00020 00021 00022 // 00023 // Define the "special" processor bus used by all machines that run a 00024 // DECchip 21264. The processor bus is used to access the internal 00025 // performance counters. 00026 // 00027 00028 #define PROCESSOR_BUS_21264 21264 00029 00030 // 00031 // Define the physical address bit that turns on user-mode access 00032 // to I/O space in the pfn of a pte. This bit is required because of 00033 // the current 36 bit physical address space limit on NT. 00034 // 00035 00036 #define EV6_USER_IO_ADDRESS_SPACE (ULONGLONG)(0x800000000) 00037 00038 // 00039 // Define the Ebox Internal Processor Register formats. 00040 // 00041 00042 // 00043 // Define the CC_CTL. 00044 // 00045 00046 typedef union _CC_CTL_21264{ 00047 struct { 00048 ULONGLONG Count : 32; 00049 ULONGLONG CcEna : 1; 00050 ULONGLONG Ignore : 31; 00051 } ; 00052 ULONGLONG all; 00053 } CC_CTL_21264, *PCC_CTL_21264; 00054 00055 // 00056 // Define VA_CTL. 00057 // 00058 00059 typedef union _VA_CTL_21264{ 00060 struct { 00061 ULONGLONG BigEndian : 1; 00062 ULONGLONG Va48 : 1; 00063 ULONGLONG VaForm32 : 1; 00064 ULONGLONG Mbz : 27; 00065 ULONGLONG VPtb : 34; 00066 }; 00067 ULONGLONG all; 00068 } VA_CTL_21264, *PVA_CTL_21264; 00069 00070 // 00071 // Define the Ibox Internal Processor Register formats. 00072 // 00073 00074 // 00075 // Define ITB_PTE. 00076 // 00077 00078 typedef union _ITB_PTE_21264{ 00079 struct { 00080 ULONGLONG Ignore1 : 4; 00081 ULONGLONG Asm : 1; 00082 ULONGLONG Gh : 2; 00083 ULONGLONG Ignore2 : 1; 00084 ULONGLONG Kre : 1; 00085 ULONGLONG Ere : 1; 00086 ULONGLONG Sre : 1; 00087 ULONGLONG Ure : 1; 00088 ULONGLONG Ignore3 : 1; 00089 ULONGLONG Pfn : 31; 00090 ULONGLONG Ignore4 : 20; 00091 }; 00092 ULONGLONG all; 00093 } ITB_PTE_21264, *PITB_PTE_21264; 00094 00095 // 00096 // Define EXC_ADDR 00097 // 00098 00099 typedef union _EXC_ADDR_21264{ 00100 struct{ 00101 ULONGLONG Pal : 1; 00102 ULONGLONG Raz : 1; 00103 ULONGLONG Pc : 62; 00104 }; 00105 ULONGLONG all; 00106 } EXC_ADDR_21264, *PEXC_ADDR_21264; 00107 00108 00109 00110 // 00111 // Define IER_CM - Interrupt Enable/Current Mode Register 00112 // Note that this can be also be written as two independant registers. 00113 // 00114 00115 typedef union _IER_CM_21264{ 00116 struct { 00117 ULONGLONG Raz1 : 3; 00118 ULONGLONG Cm : 2; 00119 ULONGLONG Raz2 : 8; 00120 ULONGLONG AstEn : 1; 00121 ULONGLONG SiEn : 15; 00122 ULONGLONG PcEn : 2; 00123 ULONGLONG CrEn : 1; 00124 ULONGLONG SlEn : 1; 00125 ULONGLONG EiEn : 6; 00126 ULONGLONG Raz3 : 25; 00127 }; 00128 ULONGLONG all; 00129 } IER_CM_21264, *PIER_CM_21264; 00130 00131 // 00132 // Define SIRR - Software Interrupt Request Register 00133 // 00134 00135 typedef union _SIRR_21264{ 00136 struct{ 00137 ULONGLONG Raz1 : 14; 00138 ULONGLONG Sir : 15; 00139 ULONGLONG Raz2 : 35; 00140 }; 00141 ULONGLONG all; 00142 } SIRR_21264, *PSIRR_21264; 00143 00144 // 00145 // Define ISUM - Interrupt Summary register 00146 // 00147 00148 typedef union _ISUM_21264{ 00149 struct{ 00150 ULONGLONG Raz1 : 3; 00151 ULONGLONG AstK : 1; 00152 ULONGLONG AstE : 1; 00153 ULONGLONG Raz2 : 4; 00154 ULONGLONG AstS : 1; 00155 ULONGLONG AstU : 1; 00156 ULONGLONG Raz3 : 3; 00157 ULONGLONG Si : 15; 00158 ULONGLONG Pc : 2; 00159 ULONGLONG Cr : 1; 00160 ULONGLONG Sl : 1; 00161 ULONGLONG Ei : 6; 00162 ULONGLONG Raz4 : 25; 00163 }; 00164 ULONGLONG all; 00165 } ISUM_21264, *PISUM_21264; 00166 00167 // 00168 // Define HW_INT_CLR - Hardware Interrupt Clear Register 00169 // 00170 00171 typedef union _HW_INT_CLR_21264{ 00172 struct{ 00173 ULONGLONG Ign1 : 26; 00174 ULONGLONG Fbtp : 1; 00175 ULONGLONG Fbdp : 1; 00176 ULONGLONG MchkD : 1; 00177 ULONGLONG Pc : 2; 00178 ULONGLONG Cr : 1; 00179 ULONGLONG Sl : 1; 00180 ULONGLONG Ign2 : 31; 00181 }; 00182 ULONGLONG all; 00183 } HW_INT_CLR_21264, *PHW_INT_CLR_21264; 00184 00185 // 00186 // Define EXC_SUM - Exception Summary Register 00187 // 00188 00189 typedef union _EXC_SUM_21264{ 00190 struct{ 00191 ULONGLONG Swc : 1; 00192 ULONGLONG Inv : 1; 00193 ULONGLONG Dze : 1; 00194 ULONGLONG Fov : 1; 00195 ULONGLONG Unf : 1; 00196 ULONGLONG Ine : 1; 00197 ULONGLONG Iov : 1; 00198 ULONGLONG Int : 1; 00199 ULONGLONG Reg : 5; 00200 ULONGLONG BadIva : 1; 00201 ULONGLONG Ignore1 : 27; 00202 ULONGLONG PcOvf : 1; 00203 ULONGLONG SetInv : 1; 00204 ULONGLONG SetDze : 1; 00205 ULONGLONG SetOvf : 1; 00206 ULONGLONG SetUnf : 1; 00207 ULONGLONG SetIne : 1; 00208 ULONGLONG SetIov : 1; 00209 ULONGLONG Ignore2 : 16; 00210 }; 00211 ULONGLONG all; 00212 } EXC_SUM_21264, *PEXC_SUM_21264; 00213 00214 // 00215 // Define I_CTL - Ibox Control Register 00216 // 00217 00218 typedef union _I_CTL_21264{ 00219 struct{ 00220 ULONGLONG PcEn : 1; 00221 ULONGLONG IcEnable : 2; 00222 ULONGLONG Sp32 : 1; 00223 ULONGLONG Sp43 : 1; 00224 ULONGLONG Sp48 : 1; 00225 ULONGLONG Raz1 : 1; 00226 ULONGLONG Sde : 1; 00227 ULONGLONG Sbe : 2; 00228 ULONGLONG BpMode : 2; 00229 ULONGLONG Hwe : 1; 00230 ULONGLONG Fbtp : 1; 00231 ULONGLONG Fbdp : 1; 00232 ULONGLONG Va48 : 1; 00233 ULONGLONG VaForm32 : 1; 00234 ULONGLONG SingleIssue : 1; 00235 ULONGLONG Pct0En : 1; 00236 ULONGLONG Pct1En : 1; 00237 ULONGLONG CallPalR23 : 1; 00238 ULONGLONG MchkEn : 1; 00239 ULONGLONG TbMbEn : 1; 00240 ULONGLONG BistFail : 1; 00241 ULONGLONG ChipId : 6; 00242 ULONGLONG Vptb : 18; 00243 ULONGLONG Sext : 16; 00244 }; 00245 ULONGLONG all; 00246 } I_CTL_21264, *PI_CTL_21264; 00247 00248 // 00249 // Define I_STAT - Ibox Status Register 00250 // 00251 00252 typedef union _I_STAT_21264{ 00253 struct{ 00254 ULONGLONG Raz1 : 29; 00255 ULONGLONG Tpe : 1; 00256 ULONGLONG Dpe : 1; 00257 ULONGLONG Raz2 : 33; 00258 }; 00259 ULONGLONG all; 00260 } I_STAT_21264, *PI_STAT_21264; 00261 00262 // 00263 // Define PCTX - Ibox Process Context Register 00264 // Note that this can be also be written as five independant registers. 00265 // (ASN, ASTER, ASTRR, PPCE, FPE) 00266 // 00267 00268 typedef union _PCTX_21264{ 00269 struct{ 00270 ULONGLONG Raz1 : 1; 00271 ULONGLONG Ppce : 1; 00272 ULONGLONG Fpe : 1; 00273 ULONGLONG Raz2 : 2; 00274 ULONGLONG AstEr : 4; 00275 ULONGLONG AstRr : 4; 00276 ULONGLONG Raz3 : 26; 00277 ULONGLONG Asn : 8; 00278 ULONGLONG Raz4 : 17; 00279 }; 00280 ULONGLONG all; 00281 } PCTX_21264, *PPCTX_21264; 00282 00283 // 00284 // Define PCTR_CTL - Performance Counter Control Register 00285 // 00286 00287 typedef union _PCTR_CTL_21264{ 00288 struct{ 00289 ULONGLONG Sel1 : 4; 00290 ULONGLONG Sel0 : 1; 00291 ULONGLONG Raz1 : 1; 00292 ULONGLONG Pctr1 : 20; 00293 ULONGLONG Raz2 : 2; 00294 ULONGLONG Pctr0 : 20; 00295 ULONGLONG Raz3 : 16; 00296 }; 00297 ULONGLONG all; 00298 } PCTR_CTL_21264, *PPCTR_CTL_21264; 00299 00300 00301 // 00302 // Define the Mbox and Dcache Internal Processor Register formats. 00303 // 00304 00305 // 00306 // Define DTB_PTE 00307 // 00308 00309 typedef union _DTB_PTE_21264{ 00310 struct{ 00311 ULONGLONG Ignore1 : 1; 00312 ULONGLONG For : 1; 00313 ULONGLONG Fow : 1; 00314 ULONGLONG Ignore2 : 1; 00315 ULONGLONG Asm : 1; 00316 ULONGLONG Gh : 2; 00317 ULONGLONG Ignore3 : 1; 00318 ULONGLONG Kre : 1; 00319 ULONGLONG Ere : 1; 00320 ULONGLONG Sre : 1; 00321 ULONGLONG Ure : 1; 00322 ULONGLONG Kwe : 1; 00323 ULONGLONG Ewe : 1; 00324 ULONGLONG Swe : 1; 00325 ULONGLONG Uwe : 1; 00326 ULONGLONG Ignore4 : 16; 00327 ULONGLONG Pfn : 31; 00328 ULONGLONG Ignore5 : 1; 00329 }; 00330 ULONGLONG all; 00331 } DTB_PTE_21264, *PDTB_PTE_21264; 00332 00333 // 00334 // Define DTB_ASN 00335 // 00336 00337 typedef union _DTB_ASN_21264{ 00338 struct{ 00339 ULONGLONG Ignore1 : 56; 00340 ULONGLONG Asn : 8; 00341 }; 00342 ULONGLONG all; 00343 } DTB_ASN_21264, *PDTB_ASN_21264; 00344 00345 // 00346 // Define MM_STAT - MBOX Status Register 00347 // 00348 00349 typedef union _MM_STAT_21264{ 00350 struct{ 00351 ULONGLONG Wr : 1; 00352 ULONGLONG Acv : 1; 00353 ULONGLONG For : 1; 00354 ULONGLONG Fow : 1; 00355 ULONGLONG Opcode : 6; 00356 ULONGLONG DcTagPerr : 1; 00357 ULONGLONG Ignore1 : 53; 00358 }; 00359 ULONGLONG all; 00360 } MM_STAT_21264, *PMM_STAT_21264; 00361 00362 // 00363 // Define M_CTL - MBOX Control Register 00364 // 00365 00366 typedef union _M_CTL_21264{ 00367 struct{ 00368 ULONGLONG Mbz1 : 1; 00369 ULONGLONG sp32 : 1; 00370 ULONGLONG sp43 : 1; 00371 ULONGLONG sp48 : 1; 00372 ULONGLONG Mbz2 : 60; 00373 }; 00374 ULONGLONG all; 00375 } M_CTL_21264, *PM_CTL_21264; 00376 00377 // 00378 // Define DC_CTL - Dcache Control Register 00379 // 00380 00381 typedef union _DC_CTL_21264{ 00382 struct{ 00383 ULONGLONG SetEn : 2; 00384 ULONGLONG Fhit : 1; 00385 ULONGLONG Flush : 1; 00386 ULONGLONG FBadTpar : 1; 00387 ULONGLONG FBadDecc : 1; 00388 ULONGLONG DcTagParEn : 1; 00389 ULONGLONG DcDatErrEn : 1; 00390 ULONGLONG Mbz1 : 56; 00391 }; 00392 ULONGLONG all; 00393 } DC_CTL_21264, *PDC_CTL_21264; 00394 00395 // 00396 // Define DC_STAT - Dcache Status Register 00397 // 00398 00399 typedef union _DC_STAT_21264{ 00400 struct{ 00401 ULONGLONG TPerrP0 : 1; 00402 ULONGLONG TPerrP1 : 1; 00403 ULONGLONG EccErrSt : 1; 00404 ULONGLONG EccErrLd : 1; 00405 ULONGLONG Seo : 1; 00406 ULONGLONG Raz1 : 59; 00407 }; 00408 ULONGLONG all; 00409 } DC_STAT_21264, *PDC_STAT_21264; 00410 00411 00412 // 00413 // Define Cbox Internal Processor Registers. 00414 // 00415 00416 // 00417 // Define CSTAT field in CBOX read IPR 00418 // 00419 00420 typedef union _C_STAT_21264 { 00421 struct { 00422 ULONGLONG ErrorQualifier :3; 00423 ULONGLONG IstreamError :1; 00424 ULONGLONG DoubleBitError :1; 00425 ULONGLONG Reserved :59; 00426 }; 00427 ULONGLONG all; 00428 } C_STAT_21264, *PC_STAT_21264; 00429 00430 00431 // SjBfix. CBOX Register chain not defined yet. 00432 00433 00434 00435 // 00436 // Define the Interrupt Mask structure communicated between the 00437 // HAL and PALcode. 00438 // 00439 // This is the bit defintion for the IRQL fields that are stored 00440 // in the PCR IrqlTable. Keep it the same as on EV4. 00441 // 00442 00443 typedef struct _IETEntry_21264{ 00444 ULONG ApcEnable: 1; 00445 ULONG DispatchEnable: 1; 00446 ULONG PerformanceCounter0Enable: 1; 00447 ULONG PerformanceCounter1Enable: 1; 00448 ULONG CorrectableReadEnable: 1; 00449 ULONG Irq0Enable: 1; 00450 ULONG Irq1Enable: 1; 00451 ULONG Irq2Enable: 1; 00452 ULONG Irq3Enable: 1; 00453 ULONG Irq4Enable: 1; 00454 ULONG Irq5Enable: 1; 00455 ULONG Reserved: 21; 00456 } IETEntry_21264, *PIETEntry_21264; 00457 00458 // 00459 // Define the offsets and sizes of the mask sub-tables within the interrupt 00460 // mask table in the PCR. 00461 // 00462 00463 #define IRQLMASK_HDW_SUBTABLE_21264 (8) 00464 #define IRQLMASK_HDW_SUBTABLE_21264_ENTRIES (64) 00465 00466 #define IRQLMASK_SFW_SUBTABLE_21264 (0) 00467 #define IRQLMASK_SFW_SUBTABLE_21264_ENTRIES (4) 00468 00469 #define IRQLMASK_PC_SUBTABLE_21264 (4) 00470 #define IRQLMASK_PC_SUBTABLE_21264_ENTRIES (4) 00471 00472 // 00473 // HACKHACK - this should probably be in a table 00474 // 00475 #define EV6_CRD_VECTOR (25) 00476 00477 // 00478 // PALcode Event Counters for the 21264 00479 // This is the structure of the data returned by the rdcounters call pal. 00480 // 00481 00482 typedef struct _COUNTERS_21264{ 00483 ULONGLONG MachineCheckCount; 00484 ULONGLONG ArithmeticExceptionCount; 00485 ULONGLONG InterruptCount; 00486 ULONGLONG ItbMissCount; 00487 ULONGLONG DtbMissSingleCount; 00488 ULONGLONG DtbMissDoubleCount; 00489 ULONGLONG IAccvioCount; 00490 ULONGLONG DfaultCount; 00491 ULONGLONG UnalignedCount; 00492 ULONGLONG OpcdecCount; 00493 ULONGLONG FenCount; 00494 ULONGLONG ItbTnvCount; 00495 ULONGLONG DtbTnvCount; 00496 ULONGLONG PdeTnvCount; 00497 ULONGLONG FPCRCount; 00498 ULONGLONG RestCount; 00499 ULONGLONG DtbMissDouble4Count; 00500 ULONGLONG HardwareInterruptCount; 00501 ULONGLONG SoftwareInterruptCount; 00502 ULONGLONG SpecialInterruptCount; 00503 ULONGLONG HaltCount; 00504 ULONGLONG RestartCount; 00505 ULONGLONG DrainaCount; 00506 ULONGLONG RebootCount; 00507 ULONGLONG InitpalCount; 00508 ULONGLONG WrentryCount; 00509 ULONGLONG SwpirqlCount; 00510 ULONGLONG RdirqlCount; 00511 ULONGLONG DiCount; 00512 ULONGLONG EiCount; 00513 ULONGLONG SwppalCount; 00514 ULONGLONG SsirCount; 00515 ULONGLONG CsirCount; 00516 ULONGLONG RfeCount; 00517 ULONGLONG RetsysCount; 00518 ULONGLONG SwpctxCount; 00519 ULONGLONG SwpprocessCount; 00520 ULONGLONG RdmcesCount; 00521 ULONGLONG WrmcesCount; 00522 ULONGLONG TbiaCount; 00523 ULONGLONG TbisCount; 00524 ULONGLONG TbisasnCount; 00525 ULONGLONG DtbisCount; 00526 ULONGLONG RdkspCount; 00527 ULONGLONG SwpkspCount; 00528 ULONGLONG RdpsrCount; 00529 ULONGLONG RdpcrCount; 00530 ULONGLONG RdthreadCount; 00531 ULONGLONG TbimCount; 00532 ULONGLONG TbimasnCount; 00533 ULONGLONG RdcountersCount; 00534 ULONGLONG RdstateCount; 00535 ULONGLONG WrperfmonCount; 00536 ULONGLONG InitpcrCount; 00537 ULONGLONG BptCount; 00538 ULONGLONG CallsysCount; 00539 ULONGLONG ImbCount; 00540 ULONGLONG GentrapCount; 00541 ULONGLONG RdtebCount; 00542 ULONGLONG KbptCount; 00543 ULONGLONG CallkdCount; 00544 ULONGLONG AddressSpaceSwapCount; 00545 ULONGLONG AsnWrapCount; 00546 ULONGLONG EalnfixCount; 00547 ULONGLONG DalnfixCount; 00548 ULONGLONG SleepCount; 00549 ULONGLONG Misc1Count; 00550 ULONGLONG Misc2Count; 00551 ULONGLONG Misc3Count; 00552 ULONGLONG Misc4Count; 00553 ULONGLONG Misc5Count; 00554 ULONGLONG Misc6Count; 00555 ULONGLONG Misc7Count; 00556 ULONGLONG Misc8Count; 00557 ULONGLONG Misc9Count; 00558 ULONGLONG Misc10Count; 00559 ULONGLONG Misc11Count; 00560 ULONGLONG Misc12Count; 00561 ULONGLONG Misc13Count; 00562 ULONGLONG Misc14Count; 00563 ULONGLONG Misc15Count; 00564 ULONGLONG Misc16Count; 00565 ULONGLONG Misc17Count; 00566 } COUNTERS_21264, *PCOUNTERS_21264; 00567 00568 // 00569 // Types of performance counters. 00570 // 00571 00572 typedef enum _AXP21264_PCCOUNTER{ 00573 Ev6PerformanceCounter0 = 0, 00574 Ev6PerformanceCounter1 = 1, 00575 } AXP21264_PCCOUNTER, *PAXP21264_PCCOUNTER; 00576 00577 // 00578 // Mux control values 00579 // 00580 00581 typedef enum _AXP21264_PCMUXCONTROL{ 00582 // 00583 // Mux values for PCTR1: 00584 // 00585 Ev6Instructions = 0x00, 00586 Ev6CondBranches = 0x01, 00587 Ev6Mispredicts = 0x02, 00588 Ev6ITBMisses = 0x03, 00589 Ev6DTBMisses = 0x04, 00590 Ev6Unaligned = 0x05, 00591 Ev6IcacheMisses = 0x06, 00592 Ev6ReplayTraps = 0x07, 00593 Ev6LoadMisses = 0x08, 00594 Ev6DcacheMisses = 0x09, 00595 Ev6BcacheReads = 0x0a, 00596 Ev6BcacheWrites = 0x0b, 00597 Ev6SysPortReads = 0x0c, 00598 Ev6SysPortWrites = 0x0d, 00599 Ev6MBStalls = 0x0e, // SjBfix. Not documented 00600 Ev6StcStalls = 0x0f, // SjBfix. Not documented 00601 00602 // 00603 // Mux values for PCTR0: 00604 // 00605 Ev6Cycles = 0x00, 00606 Ev6RetiredInstructions = 0x01 00607 00608 } AXP21264_PCMUXCONTROL, *PAXP21264_PCMUXCONTROL; 00609 00610 00611 // 00612 // Internal processor state record. 00613 // This is the structure of the data returned by the rdstate call pal. 00614 // 00615 00616 typedef struct _PROCESSOR_STATE_21264{ 00617 IER_CM_21264 IerCm; 00618 SIRR_21264 Sirr; 00619 ISUM_21264 Isum; 00620 EXC_SUM_21264 ExcSum; 00621 ULONGLONG PalBase; 00622 I_CTL_21264 ICtl; 00623 I_STAT_21264 IStat; 00624 PCTX_21264 PCtx; 00625 PCTR_CTL_21264 PCtr; 00626 MM_STAT_21264 MmStat; 00627 DC_STAT_21264 DcStat; 00628 00629 } PROCESSOR_STATE_21264, *PPROCESSOR_STATE_21264; 00630 00631 // 00632 // Machine-check logout frame. 00633 // 00634 00635 typedef struct _LOGOUT_FRAME_21264{ 00636 ULONG FrameSize; 00637 ULONG RSDC; 00638 ULONG CpuAreaOffset; 00639 ULONG SystemAreaOffset; 00640 ULONG MchkCode; 00641 ULONG MchkFrameRev; 00642 I_STAT_21264 IStat; 00643 DC_STAT_21264 DcStat; 00644 ULONGLONG CAddr; 00645 ULONGLONG Dc1Syndrome; 00646 ULONGLONG Dc0Syndrome; 00647 ULONGLONG CStat; 00648 ULONGLONG CSts; 00649 ULONGLONG Va; 00650 ULONGLONG ExcAddr; 00651 IER_CM_21264 IerCm; 00652 ISUM_21264 ISum; 00653 MM_STAT_21264 MmStat; 00654 ULONGLONG PalBase; 00655 I_CTL_21264 ICtl; 00656 PCTX_21264 PCtx; 00657 VA_CTL_21264 VaCtl; 00658 ULONGLONG Ps; 00659 } LOGOUT_FRAME_21264, *PLOGOUT_FRAME_21264; 00660 00661 // 00662 // Correctable logout frame 00663 // 00664 00665 typedef struct _CORRECTABLE_FRAME_21264 { 00666 ULONG FrameSize; 00667 ULONG RSDC; 00668 ULONG CpuAreaOffset; 00669 ULONG SystemAreaOffset; 00670 ULONG MchkCode; 00671 ULONG MchkFrameRev; 00672 I_STAT_21264 IStat; 00673 DC_STAT_21264 DCStat; 00674 ULONGLONG CAddr; 00675 ULONGLONG Dc1Syndrome; 00676 ULONGLONG Dc0Syndrome; 00677 ULONGLONG CStat; 00678 ULONGLONG CSts; 00679 ULONGLONG MmStat; 00680 } CORRECTABLE_FRAME_21264, *PCORRECTABLE_FRAME_21264; 00681 00682 // 00683 // Define the number of physical and virtual address bits 00684 // 00685 00686 #define EV6_PHYSICAL_ADDRESS_BITS 44 00687 #define EV6_VIRTUAL_ADDRESS_BITS 43 00688 00689 #endif