kernlini.c File Reference

#include "ki.h"
#include "ki386.h"
#include "fastsys.inc"

Go to the source code of this file.

Defines
#define	TRAP332_GATE   0xEF00
#define	RET   0xc3
#define	CRC_NDX   (PUCHAR)0x22
#define	CRC_DAT   (CRC_NDX + 1)
#define	CCR1   0xc1
#define	CPUID_REG_COUNT   4
#define	MAX_ATTEMPTS   10
#define	IDT_SKIP   (7 * sizeof (KIDTENTRY))
Enumerations
enum	CPU_VENDORS {   CPU_NONE, CPU_INTEL, CPU_AMD, CPU_CYRIX,   CPU_UNKNOWN }
Functions
VOID	KiSetProcessorType (VOID)
VOID	KiSetCR0Bits (VOID)
BOOLEAN	KiIsNpxPresent (VOID)
VOID	KiI386PentiumLockErrataFixup (VOID)
VOID	KiInitializeDblFaultTSS (IN PKTSS Tss, IN ULONG Stack, IN PKGDTENTRY TssDescriptor)
VOID	KiInitializeTSS2 (IN PKTSS Tss, IN PKGDTENTRY TssDescriptor)
VOID	KiSwapIDT (VOID)
VOID	KeSetup80387OrEmulate (IN PVOID *R3EmulatorTable)
VOID	KiGetCacheInformation (VOID)
ULONG	KiGetCpuVendor (VOID)
ULONG	KiGetFeatureBits (VOID)
NTSTATUS	KiMoveRegTree (HANDLE Source, HANDLE Dest)
VOID	Ki386EnableFxsr (IN volatile PLONG Number)
VOID	Ki386EnableXMMIExceptions (IN volatile PLONG Number)
VOID	Ki386EnableGlobalPage (IN volatile PLONG Number)
VOID	Ki386UseSynchronousTbFlush (IN volatile PLONG Number)
BOOLEAN	KiInitMachineDependent (VOID)
VOID	KiInitializeMTRR (IN BOOLEAN LastProcessor)
VOID	KiInitializePAT (VOID)
VOID	KiAmdK6InitializeMTRR (VOID)
VOID FASTCALL	KiZeroPage (PVOID PageBase)
VOID FASTCALL	KiXMMIZeroPage (PVOID PageBase)
VOID FASTCALL	KiXMMIZeroPageNoSave (PVOID PageBase)
VOID	KiInitializeKernel (IN PKPROCESS Process, IN PKTHREAD Thread, IN PVOID IdleStack, IN PKPRCB Prcb, IN CCHAR Number, PLOADER_PARAMETER_BLOCK LoaderBlock)
VOID	KiInitializePcr (IN ULONG Processor, IN PKPCR Pcr, IN PKIDTENTRY Idt, IN PKGDTENTRY Gdt, IN PKTSS Tss, IN PKTHREAD Thread, IN PVOID DpcStack)
VOID	KiInitializeTSS (IN PKTSS Tss)
VOID	KiSwapIDT ()
VOID	KeOptimizeProcessorControlState (VOID)
Variables
KSPIN_LOCK	CcMasterSpinLock
KSPIN_LOCK	CcVacbSpinLock
KSPIN_LOCK	MmPfnLock
KSPIN_LOCK	MmSystemSpaceLock
BOOLEAN	KiI386PentiumLockErrataPresent = FALSE
BOOLEAN	KiIgnoreUnexpectedTrap07 = FALSE
PVOID	Ki387RoundModeTable
PVOID	Ki386IopmSaveArea
ULONG	KeI386ForceNpxEmulation
WCHAR	CmDisabledFloatingPointProcessor []
UCHAR	CmpCyrixID []
UCHAR	CmpIntelID []
UCHAR	CmpAmdID []
PVOID	ScPatchFxb
PVOID	ScPatchFxe
BOOLEAN	KeI386XMMIPresent
KE_ZERO_PAGE_ROUTINE	KeZeroPage = KiZeroPage
KE_ZERO_PAGE_ROUTINE	KeZeroPageFromIdleThread = KiZeroPage
ULONG	Ki486CompatibilityLock
KIDTENTRY	IDT []

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Define Documentation

#define CCR1   0xc1

#define CPUID_REG_COUNT   4

Referenced by KiGetCacheInformation().

#define CRC_DAT   (CRC_NDX + 1)

#define CRC_NDX   (PUCHAR)0x22

#define IDT_SKIP   (7 * sizeof (KIDTENTRY))

Referenced by KiI386PentiumLockErrataFixup().

#define MAX_ATTEMPTS   10

Definition at line 1688 of file kernlini.c. Referenced by KiInitMachineDependent(), and WinHelpA().

#define RET   0xc3

Referenced by KiInitializeKernel().

#define TRAP332_GATE   0xEF00

Definition at line 41 of file kernlini.c. Referenced by KeSetup80387OrEmulate().

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Enumeration Type Documentation

enum CPU_VENDORS

Enumeration values: CPU_NONE  CPU_INTEL  CPU_AMD  CPU_CYRIX  CPU_UNKNOWN  Definition at line 194 of file kernlini.c. { CPU_NONE, CPU_INTEL, CPU_AMD, CPU_CYRIX, CPU_UNKNOWN } CPU_VENDORS;

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Function Documentation

VOID KeOptimizeProcessorControlState (  VOID   )

Definition at line 1998 of file kernlini.c. References Ke386ConfigureCyrixProcessor(). Referenced by CmpConfigureProcessors(). { Ke386ConfigureCyrixProcessor (); }

VOID KeSetup80387OrEmulate (  IN PVOID *  R3EmulatorTable  )

Definition at line 2008 of file kernlini.c. References CmDisabledFloatingPointProcessor, CmRegistryMachineHardwareDescriptionSystemName, CmTypeName, Compare(), FALSE, FloatingPointProcessor, is, it, KeActiveProcessors, KeFeatureBits, KeGetPcr, KeI386ForceNpxEmulation, KeI386NpxPresent, KeRevertToUserAffinityThread(), KeSetSystemAffinityThread(), KF_FXSR, KF_MMX, KF_XMMI, Ki387RoundModeTable, KiLockDispatcherDatabase, KiMoveRegTree(), KiUnlockDispatcherDatabase(), move, NT_SUCCESS, NTSTATUS(), NULL, ObjectAttributes, RtlInitUnicodeString(), Status, the, TRAP332_GATE, and TRUE. Referenced by PspInitializeSystemDll(). : This routine is called by PS initialization after loading NTDLL. If this is a 386 system without 387s (all processors must be symmetrical) then this function will set the trap 07 vector on all processors to point to the address passed in (which should be the entry point of the 80387 emulator in NTDLL, NPXNPHandler). Arguments: HandlerAddress - Supplies the address of the trap07 handler. Return Value: None. --*/ { PKINTERRUPT_ROUTINE HandlerAddress; KAFFINITY ActiveProcessors, CurrentAffinity; KIRQL OldIrql; ULONG disposition; HANDLE SystemHandle, SourceHandle, DestHandle; NTSTATUS Status; UNICODE_STRING unicodeString; OBJECT_ATTRIBUTES ObjectAttributes; double Dividend, Divisor; BOOLEAN PrecisionErrata; if (KeI386NpxPresent) { // // A coprocessor is present - check to see if the precision errata exists // PrecisionErrata = FALSE; ActiveProcessors = KeActiveProcessors; for (CurrentAffinity = 1; ActiveProcessors; CurrentAffinity <<= 1) { if (ActiveProcessors & CurrentAffinity) { ActiveProcessors &= ~CurrentAffinity; // // Run calculation on each processor. // KeSetSystemAffinityThread(CurrentAffinity); _asm { ; ; This is going to destroy the state in the coprocesssor, ; but we know that there's no state currently in it. ; cli mov eax, cr0 mov ecx, eax ; hold original cr0 value and eax, not (CR0_TS+CR0_MP+CR0_EM) mov cr0, eax fninit ; to known state } Dividend = 4195835.0; Divisor = 3145727.0; _asm { fld Dividend fdiv Divisor ; test known faulty divison fmul Divisor ; Multiple quotient by divisor fcomp Dividend ; Compare product and dividend fstsw ax ; Move float conditions to ax sahf ; move to eflags mov cr0, ecx ; restore cr0 sti jc short em10 jz short em20 em10: mov PrecisionErrata, TRUE em20: } } } // // Check to see if the emulator should be used anyway // switch (KeI386ForceNpxEmulation) { case 0: // // Use the emulator based on the value in KeI386NpxPresent // break; case 1: // // Only use the emulator if any processor has the known // Pentium floating point division problem. // if (PrecisionErrata) { KeI386NpxPresent = FALSE; } break; default: // // Unknown setting - use the emulator // KeI386NpxPresent = FALSE; break; } } // // Setup processor features, and install emulator if needed // SharedUserData->ProcessorFeatures[PF_FLOATING_POINT_EMULATED] = !KeI386NpxPresent; SharedUserData->ProcessorFeatures[PF_FLOATING_POINT_PRECISION_ERRATA] = PrecisionErrata; if (!KeI386NpxPresent) { // // MMx not available when emulator is used // KeFeatureBits &= ~(KF_MMX|KF_FXSR|KF_XMMI); SharedUserData->ProcessorFeatures[PF_MMX_INSTRUCTIONS_AVAILABLE] = FALSE; SharedUserData->ProcessorFeatures[PF_XMMI_INSTRUCTIONS_AVAILABLE] = FALSE; SharedUserData->ProcessorFeatures[PF_3DNOW_INSTRUCTIONS_AVAILABLE] = FALSE; // // Errata not present when using emulator // SharedUserData->ProcessorFeatures[PF_FLOATING_POINT_PRECISION_ERRATA] = FALSE; // // Use the user mode floating point emulator // HandlerAddress = (PKINTERRUPT_ROUTINE) ((PULONG) R3EmulatorTable)[0]; Ki387RoundModeTable = (PVOID) ((PULONG) R3EmulatorTable)[1]; ActiveProcessors = KeActiveProcessors; for (CurrentAffinity = 1; ActiveProcessors; CurrentAffinity <<= 1) { if (ActiveProcessors & CurrentAffinity) { ActiveProcessors &= ~CurrentAffinity; // // Run this code on each processor. // KeSetSystemAffinityThread(CurrentAffinity); // // Raise IRQL and lock dispatcher database. // KiLockDispatcherDatabase(&OldIrql); // // Make the trap 07 IDT entry point at the passed-in handler // KiSetHandlerAddressToIDT(I386_80387_NP_VECTOR, HandlerAddress); KeGetPcr()->IDT[I386_80387_NP_VECTOR].Selector = KGDT_R3_CODE; KeGetPcr()->IDT[I386_80387_NP_VECTOR].Access = TRAP332_GATE; // // Unlock dispatcher database and lower IRQL to its previous value. // KiUnlockDispatcherDatabase(OldIrql); } } // // Move any entries from ..\System\FloatingPointProcessor to // ..\System\DisabledFloatingPointProcessor. // // // Open system tree // InitializeObjectAttributes( &ObjectAttributes, &CmRegistryMachineHardwareDescriptionSystemName, OBJ_CASE_INSENSITIVE, NULL, NULL ); Status = ZwOpenKey( &SystemHandle, KEY_ALL_ACCESS, &ObjectAttributes ); if (NT_SUCCESS(Status)) { // // Open FloatingPointProcessor key // InitializeObjectAttributes( &ObjectAttributes, &CmTypeName[FloatingPointProcessor], OBJ_CASE_INSENSITIVE, SystemHandle, NULL ); Status = ZwOpenKey ( &SourceHandle, KEY_ALL_ACCESS, &ObjectAttributes ); if (NT_SUCCESS(Status)) { // // Create DisabledFloatingPointProcessor key // RtlInitUnicodeString ( &unicodeString, CmDisabledFloatingPointProcessor ); InitializeObjectAttributes( &ObjectAttributes, &unicodeString, OBJ_CASE_INSENSITIVE, SystemHandle, NULL ); Status = ZwCreateKey( &DestHandle, KEY_ALL_ACCESS, &ObjectAttributes, 0, NULL, REG_OPTION_VOLATILE, &disposition ); if (NT_SUCCESS(Status)) { // // Move it // KiMoveRegTree (SourceHandle, DestHandle); ZwClose (DestHandle); } ZwClose (SourceHandle); } ZwClose (SystemHandle); } } // // Set affinity back to the original value. // KeRevertToUserAffinityThread(); }

VOID Ki386EnableFxsr (  IN volatile PLONG  Number  )

Referenced by KiInitMachineDependent().

VOID Ki386EnableGlobalPage (  IN volatile PLONG  Number  )

Referenced by KiInitMachineDependent().

VOID Ki386EnableXMMIExceptions (  IN volatile PLONG  Number  )

Referenced by KiInitMachineDependent().

VOID Ki386UseSynchronousTbFlush (  IN volatile PLONG  Number  )

VOID KiAmdK6InitializeMTRR (  VOID   )

Definition at line 168 of file mtrramd.c. References AMDK6_MTRR_MSR, AMDK6_MTRR_TYPE_DISABLED, AMDK6_REGION_UNUSED, AmdK6RegionCount, AmdK6Regions, AmdMtrrHwUsageCount, _AMDK6_MTRR_REGION::BaseAddress, DBGMSG, KeAcquireSpinLock, KeInitializeSpinLock(), KeReleaseSpinLock(), KiAmdK6Mtrr, KiAmdK6MTRRAddRegionFromHW(), KiRangeLock, MAX_K6_REGIONS, RDMSR(), _AMDK6_MTRR_REGION::RegionFlags, and _AMDK6_MTRR_MSR_IMAGE::u. { ULONG i; KIRQL OldIrql; DBGMSG("KiAmdK6InitializeMTRR: Initializing K6 MTRR support\n"); KiAmdK6Mtrr.u.hw.mtrr0.type = AMDK6_MTRR_TYPE_DISABLED; KiAmdK6Mtrr.u.hw.mtrr1.type = AMDK6_MTRR_TYPE_DISABLED; AmdK6RegionCount = MAX_K6_REGIONS; AmdMtrrHwUsageCount = 0; // // Set all regions to free. // for (i = 0; i < AmdK6RegionCount; i++) { AmdK6Regions[i].BaseAddress = AMDK6_REGION_UNUSED; AmdK6Regions[i].RegionFlags = 0; } // // Initialize the spin lock. // // N.B. Normally this is done by KiInitializeMTRR but that // routine is not called in the AMD K6 case. // KeInitializeSpinLock (&KiRangeLock); // // Read the MTRR registers to see if the BIOS has set them up. // If so, add entries to the region table and adjust the usage // count. Serialize the region table. // KeAcquireSpinLock (&KiRangeLock, &OldIrql); KiAmdK6Mtrr.u.QuadPart = RDMSR (AMDK6_MTRR_MSR); // // Check MTRR0 first. // KiAmdK6MTRRAddRegionFromHW(KiAmdK6Mtrr.u.hw.mtrr0); // // Now check MTRR1. // KiAmdK6MTRRAddRegionFromHW(KiAmdK6Mtrr.u.hw.mtrr1); // // Release the locks. // KeReleaseSpinLock (&KiRangeLock, OldIrql); }

VOID KiGetCacheInformation (  VOID   )

Definition at line 1509 of file kernlini.c. References ASSERT, CPU_AMD, CPU_INTEL, CPU_NONE, CPUID(), CPUID_REG_COUNT, FALSE, KeGetPcr, KiGetCpuVendor(), and TRUE. Referenced by KiInitializeKernel(). { #define CPUID_REG_COUNT 4 ULONG CpuidData[CPUID_REG_COUNT]; ULONG CpuVendor; PKPCR Pcr; // // Set default. // Pcr = KeGetPcr(); Pcr->SecondLevelCacheSize = 0; // // Determine the processor manufacturer // CpuVendor = KiGetCpuVendor(); if (CpuVendor == CPU_NONE) { return; } // // Obtain Cache size information for those processors on which // we know how. // switch (CpuVendor) { case CPU_INTEL: CPUID(0, CpuidData, CpuidData+1, CpuidData+2, CpuidData+3); // // Check this processor supports CPUID function 2 which is the // one that returns cache size info. // if (CpuidData[0] >= 2) { // // The above returns a series of bytes. (In EAX, EBX, ECX // and EDX). The least significant byte (of EAX) gives the // number of times CPUID(2 ...) should be issued to return // the complete set of data. The bytes are self describing // data. // // In particular, the bytes describing the L2 cache size // will be in the following set (and meaning) // // 0x40 0 bytes // 0x41 128K bytes // 0x42 256K bytes // 0x43 512K bytes // 0x44 1024K bytes // 0x45 2048K bytes // 0x46 4096K bytes // // I am extrapolating the above as anything in the range // 0x41 thru 0x4f can be computed as // // 128KB << (descriptor - 0x41) // // The Intel folks say keep it to a reasonable upper bound, // eg 49. // // N.B. the range 0x80 .. 0x86 indicates the same cache // sizes but 8 way associative. // // Also, the most significant bit of each register indicates // whether not the register contains valid information. // 0 == Valid, 1 == InValid. // ULONG CpuidIterations; ULONG i; ULONG CpuidReg; BOOLEAN FirstPass = TRUE; do { CPUID(2, CpuidData, CpuidData+1, CpuidData+2, CpuidData+3); if (FirstPass) { // // Get the iteration count from the first byte // of the returned data then replace that byte // with 0 (a null descriptor). // CpuidIterations = CpuidData[0] & 0xff; CpuidData[0] &= 0xffffff00; FirstPass = FALSE; } for (i = 0; i < CPUID_REG_COUNT; i++) { CpuidReg = CpuidData[i]; if (CpuidReg & 0x80000000) { // // Register doesn't contain valid data, // skip it. // continue; } while (CpuidReg) { // // Get LS Byte from this DWORD and remove the // byte. // UCHAR Descriptor = (UCHAR)(CpuidReg & 0xff); CpuidReg >>= 8; if (Descriptor == 0) { // // NULL descriptor // continue; } if (((Descriptor > 0x40) && (Descriptor <= 0x49)) || ((Descriptor > 0x80) && (Descriptor <= 0x89))) { // // L2 descriptor. // Descriptor &= 0x0f; // // Assert the descriptor is in the range we // officially know about. If this hits on // a checked build, check with Intel about // the interpretation. // ASSERT(Descriptor <= 0x6); Pcr->SecondLevelCacheSize = 0x10000 << Descriptor; } // // else if (do other descriptors) // } // while more bytes in this register } // for each register // // Note: Always run thru all iterations indicated by // the first to ensure a subsequent call won't start // part way thru. // } while (--CpuidIterations); } break; case CPU_AMD: break; } #undef CPUID_REG_COUNT }

ULONG KiGetCpuVendor (  VOID   )

Definition at line 1110 of file kernlini.c. References Buffer, CmpAmdID, CmpCyrixID, CmpIntelID, CPU_AMD, CPU_CYRIX, CPU_INTEL, CPU_NONE, CPU_UNKNOWN, CPUID(), and KeGetCurrentPrcb. Referenced by KiGetCacheInformation(). 01116 : 01117 01118 (Try to) Determine the manufacturer of this processor based on 01119 data returned by the CPUID instruction (if present). 01120 01121 Arguments: 01122 01123 None. 01124 01125 Return Value: 01126 01127 One of the members of the enumeration CPU_VENDORS (defined above). 01128 01129 --*/ 01130 { 01131 PKPRCB Prcb; 01132 ULONG Junk; 01133 ULONG Buffer[4]; 01134 01135 Prcb = KeGetCurrentPrcb(); 01136 Prcb->VendorString[0] = 0; 01137 01138 if (!Prcb->CpuID) { 01139 return CPU_NONE; 01140 } 01141 01142 CPUID(0, &Junk, Buffer+0, Buffer+2, Buffer+1); 01143 Buffer[3] = 0; 01144 01145 // 01146 // Copy vendor string to Prcb for debugging (ensure it's NULL 01147 // terminated). 01148 // 01149 01150 RtlCopyMemory( 01151 Prcb->VendorString, 01152 Buffer, 01153 sizeof(Prcb->VendorString) - 1 01154 ); 01155 01156 Prcb->VendorString[sizeof(Prcb->VendorString) - 1] = '\0'; 01157 01158 if (strcmp((PVOID)Buffer, CmpIntelID) == 0) { 01159 return CPU_INTEL; 01160 } else if (strcmp((PVOID)Buffer, CmpAmdID) == 0) { 01161 return CPU_AMD; 01162 } else if (strcmp((PVOID)Buffer, CmpCyrixID) == 0) { 01163 return CPU_CYRIX; 01164 } 01165 return CPU_UNKNOWN; 01166 }

ULONG KiGetFeatureBits (  VOID   )

Referenced by KiInitializeKernel().

VOID KiI386PentiumLockErrataFixup (  VOID   )

Definition at line 2460 of file kernlini.c. References ASSERT, IDT_SKIP, KeGetPcr, KiDisableInterrupts(), KiRestoreInterrupts(), MmAllocateIndependentPages(), MmSetPageProtection(), PAGE_SIZE, and Status. Referenced by KiInitMachineDependent(). 02466 : 02467 02468 This routine is called once on every processor when 02469 KiI386PentiumLockErrataPresent is TRUE. 02470 02471 This routine replaces the local IDT with an IDT that has the first 7 IDT 02472 entries on their own page and returns the first page to the caller to 02473 be marked as read-only. This causes the processor to trap-0e fault when 02474 the errata occurs. Special code in the trap-0e handler detects the 02475 problem and performs the proper fixup. 02476 02477 Arguments: 02478 02479 FixupPage - Returns a virtual address of a page to be marked read-only 02480 02481 Return Value: 02482 02483 None. 02484 02485 --*/ 02486 02487 { 02488 KDESCRIPTOR IdtDescriptor; 02489 ULONG OrginalBase; 02490 PUCHAR NewBase, BasePage; 02491 BOOLEAN Enable; 02492 BOOLEAN Status; 02493 02494 02495 #define IDT_SKIP (7 * sizeof (KIDTENTRY)) 02496 02497 // 02498 // Allocate memory for a new copy of the processors IDT 02499 // 02500 02501 BasePage = MmAllocateIndependentPages (2*PAGE_SIZE); 02502 02503 // 02504 // The IDT base is such that the first 7 entries are on the 02505 // first (read-only) page, and the remaining entries are on the 02506 // second (read-write) page 02507 // 02508 02509 NewBase = BasePage + PAGE_SIZE - IDT_SKIP; 02510 02511 // 02512 // Disable interrupts on this processor while updating the IDT base 02513 // 02514 02515 Enable = KiDisableInterrupts(); 02516 02517 // 02518 // Copy Old IDT to new IDT 02519 // 02520 02521 _asm { 02522 sidt IdtDescriptor.Limit 02523 } 02524 02525 RtlMoveMemory ((PVOID) NewBase, 02526 (PVOID) IdtDescriptor.Base, 02527 IdtDescriptor.Limit + 1 02528 ); 02529 02530 IdtDescriptor.Base = (ULONG) NewBase; 02531 02532 // 02533 // Set the new IDT 02534 // 02535 02536 _asm { 02537 lidt IdtDescriptor.Limit 02538 } 02539 02540 // 02541 // Update the PCR 02542 // 02543 02544 KeGetPcr()->IDT = (PKIDTENTRY) NewBase; 02545 02546 // 02547 // Restore interrupts 02548 // 02549 02550 KiRestoreInterrupts(Enable); 02551 02552 // 02553 // Mark the first page which contains IDT entries 0-6 as read-only 02554 // 02555 02556 Status = MmSetPageProtection (BasePage, PAGE_SIZE, PAGE_READONLY); 02557 ASSERT (Status); 02558 } }

VOID KiInitializeDblFaultTSS (  IN PKTSS  Tss, IN ULONG  Stack, IN PKGDTENTRY  TssDescriptor )

VOID KiInitializeKernel (  IN PKPROCESS  Process, IN PKTHREAD  Thread, IN PVOID  IdleStack, IN PKPRCB  Prcb, IN CCHAR  Number, PLOADER_PARAMETER_BLOCK  LoaderBlock )

Definition at line 246 of file kernlini.c. References APC_LEVEL, CcMasterSpinLock, CcVacbSpinLock, DISPATCH_LEVEL, ExAllocatePoolWithTag, EXCEPTION_EXECUTE_HANDLER, ExpInitializeExecutive(), FALSE, HIGH_LEVEL, Index, KeBugCheck(), KeBugCheckEx(), KeFeatureBits, KeGetPcr, KeI386CpuStep, KeI386CpuType, KeI386FxsrPresent, KeI386NpxPresent, KeI386XMMIPresent, KeInitializeProcess(), KeInitializeSpinLock(), KeInitializeThread(), KeLowerIrql(), KeMaximumIncrement, KeProcessorArchitecture, KeProcessorLevel, KeProcessorRevision, KeRaiseIrql(), KeReleaseSpinLock(), KeSetPriorityThread(), KF_3DNOW, KF_CMPXCHG8B, KF_FXSR, KF_GLOBAL_PAGE, KF_MMX, KF_MTRR, KF_PAT, KF_RDTSC, KF_XMMI, Ki386IopmSaveArea, Ki486CompatibilityLock, KiAdjustDpcThreshold, KiBootFeatureBits, KiComputeReciprocal(), KiContextSwapLock, KiDispatcherLock, KiFreezeExecutionLock, KiGetCacheInformation(), KiGetFeatureBits(), KiIdleSummary, KiInitSystem(), KiIsNpxPresent(), KiMaximumDpcQueueDepth, KiMinimumDpcRate, KiQueuedSpinLockContext, KiSetCR0Bits(), KiSetProcessorType(), KiTimeIncrementReciprocal, KiTimeIncrementShiftCount, KiTryToAcquireQueuedSpinLock(), LockQueueContextSwapLock, LockQueueDispatcherLock, LockQueueMasterLock, LockQueuePfnLock, LockQueueSystemSpaceLock, LockQueueVacbLock, MmCreateKernelStack(), MmPfnLock, MmSystemSpaceLock, NULL, PAGE_SIZE, PagedPool, PKSTART_ROUTINE, PKSYSTEM_ROUTINE, PoInitializePrcb(), _LOADER_PARAMETER_BLOCK::Prcb, RET, Running, SetMember, TRUE, and USHORT. 00257 : 00258 00259 This function gains control after the system has been bootstrapped and 00260 before the system has been initialized. Its function is to initialize 00261 the kernel data structures, initialize the idle thread and process objects, 00262 initialize the processor control block, call the executive initialization 00263 routine, and then return to the system startup routine. This routine is 00264 also called to initialize the processor specific structures when a new 00265 processor is brought on line. 00266 00267 Arguments: 00268 00269 Process - Supplies a pointer to a control object of type process for 00270 the specified processor. 00271 00272 Thread - Supplies a pointer to a dispatcher object of type thread for 00273 the specified processor. 00274 00275 IdleStack - Supplies a pointer the base of the real kernel stack for 00276 idle thread on the specified processor. 00277 00278 Prcb - Supplies a pointer to a processor control block for the specified 00279 processor. 00280 00281 Number - Supplies the number of the processor that is being 00282 initialized. 00283 00284 LoaderBlock - Supplies a pointer to the loader parameter block. 00285 00286 Return Value: 00287 00288 None. 00289 00290 --*/ 00291 00292 { 00293 LONG Index; 00294 ULONG DirectoryTableBase[2]; 00295 KIRQL OldIrql; 00296 PKPCR Pcr; 00297 BOOLEAN NpxFlag; 00298 BOOLEAN FxsrPresent; 00299 BOOLEAN XMMIPresent; 00300 ULONG FeatureBits; 00301 00302 KiSetProcessorType(); 00303 KiSetCR0Bits(); 00304 NpxFlag = KiIsNpxPresent(); 00305 00306 Pcr = KeGetPcr(); 00307 00308 // 00309 // Initialize DPC listhead and lock. 00310 // 00311 00312 InitializeListHead(&Prcb->DpcListHead); 00313 KeInitializeSpinLock(&Prcb->DpcLock); 00314 Prcb->DpcRoutineActive = 0; 00315 Prcb->DpcQueueDepth = 0; 00316 Prcb->MaximumDpcQueueDepth = KiMaximumDpcQueueDepth; 00317 Prcb->MinimumDpcRate = KiMinimumDpcRate; 00318 Prcb->AdjustDpcThreshold = KiAdjustDpcThreshold; 00319 PoInitializePrcb (Prcb); 00320 00321 // 00322 // Check for unsupported processor revision 00323 // 00324 00325 if (Prcb->CpuType == 3) { 00326 KeBugCheckEx(UNSUPPORTED_PROCESSOR,0x386,0,0,0); 00327 } 00328 00329 // 00330 // Get the processor FeatureBits for this processor. 00331 // 00332 00333 FeatureBits = KiGetFeatureBits(); 00334 Prcb->FeatureBits = FeatureBits; 00335 00336 // 00337 // Get processor Cache Size information. 00338 // 00339 00340 KiGetCacheInformation(); 00341 00342 // 00343 // initialize the per processor lock queue entry for implemented locks. 00344 // 00345 00346 #if !defined(NT_UP) 00347 00348 Prcb->LockQueue[LockQueueDispatcherLock].Next = NULL; 00349 Prcb->LockQueue[LockQueueDispatcherLock].Lock = &KiDispatcherLock; 00350 Prcb->LockQueue[LockQueueContextSwapLock].Next = NULL; 00351 Prcb->LockQueue[LockQueueContextSwapLock].Lock = &KiContextSwapLock; 00352 Prcb->LockQueue[LockQueuePfnLock].Next = NULL; 00353 Prcb->LockQueue[LockQueuePfnLock].Lock = &MmPfnLock; 00354 Prcb->LockQueue[LockQueueSystemSpaceLock].Next = NULL; 00355 Prcb->LockQueue[LockQueueSystemSpaceLock].Lock = &MmSystemSpaceLock; 00356 Prcb->LockQueue[LockQueueMasterLock].Next = NULL; 00357 Prcb->LockQueue[LockQueueMasterLock].Lock = &CcMasterSpinLock; 00358 Prcb->LockQueue[LockQueueVacbLock].Next = NULL; 00359 Prcb->LockQueue[LockQueueVacbLock].Lock = &CcVacbSpinLock; 00360 00361 #endif 00362 00363 // 00364 // If the initial processor is being initialized, then initialize the 00365 // per system data structures. 00366 // 00367 00368 if (Number == 0) { 00369 00370 // 00371 // Initial setting for global Cpu & Stepping levels 00372 // 00373 00374 KeI386NpxPresent = NpxFlag; 00375 KeI386CpuType = Prcb->CpuType; 00376 KeI386CpuStep = Prcb->CpuStep; 00377 00378 KeProcessorArchitecture = PROCESSOR_ARCHITECTURE_INTEL; 00379 KeProcessorLevel = (USHORT)Prcb->CpuType; 00380 if (Prcb->CpuID == 0) { 00381 KeProcessorRevision = 0xFF00 | 00382 (((Prcb->CpuStep >> 4) + 0xa0 ) & 0x0F0) | 00383 (Prcb->CpuStep & 0xf); 00384 } else { 00385 KeProcessorRevision = Prcb->CpuStep; 00386 } 00387 00388 KeFeatureBits = FeatureBits; 00389 00390 KeI386FxsrPresent = ((KeFeatureBits & KF_FXSR) ? TRUE:FALSE); 00391 00392 KeI386XMMIPresent = ((KeFeatureBits & KF_XMMI) ? TRUE:FALSE); 00393 00394 // 00395 // If cmpxchg8b was available at boot, verify its still available 00396 // 00397 00398 if ((KiBootFeatureBits & KF_CMPXCHG8B) && !(KeFeatureBits & KF_CMPXCHG8B)) { 00399 KeBugCheckEx (MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED, KF_CMPXCHG8B, 0, 0, 0); 00400 } 00401 00402 // 00403 // Lower IRQL to APC level. 00404 // 00405 00406 KeLowerIrql(APC_LEVEL); 00407 00408 00409 // 00410 // Initialize kernel internal spinlocks 00411 // 00412 00413 KeInitializeSpinLock(&KiContextSwapLock); 00414 KeInitializeSpinLock(&KiDispatcherLock); 00415 KeInitializeSpinLock(&KiFreezeExecutionLock); 00416 00417 // 00418 // Initialize 486 compatibility lock 00419 // 00420 00421 KeInitializeSpinLock(&Ki486CompatibilityLock); 00422 00423 #if !defined(NT_UP) 00424 00425 // 00426 // During Text Mode setup, it is possible the system is 00427 // running with an MP kernel and a UP HAL. On X86 systems, 00428 // spinlocks are implemented in both the kernel and the HAL 00429 // with the verisons that alter IRQL in the HAL. If the 00430 // HAL is UP, it will not actually acquire/release locks 00431 // while the MP kernel will which will cause the system to 00432 // hang (or crash). As this can only occur during text 00433 // mode setup, we will detect the situation and disable 00434 // the kernel only versions of queued spinlocks if the HAL 00435 // is UP (and the kernel MP). 00436 // 00437 // We need to patch 3 routines, two of them are void and 00438 // the other returns a boolean (must be true (and ZF must be 00439 // clear) in a UP case). 00440 // 00441 // Determine if the HAL us UP by acquiring the dispatcher 00442 // lock and examining it to see if the HAL actually did 00443 // anything to it. 00444 // 00445 00446 OldIrql = KfAcquireSpinLock(&KiDispatcherLock); 00447 if (KiDispatcherLock == 0) { 00448 00449 // 00450 // KfAcquireSpinLock is in the HAL and it did not 00451 // change the value of the lock. This is a UP HAL. 00452 // 00453 00454 extern UCHAR KiTryToAcquireQueuedSpinLockUP; 00455 PUCHAR PatchTarget, PatchSource; 00456 UCHAR Byte; 00457 00458 #define RET 0xc3 00459 00460 *(PUCHAR)(KiAcquireQueuedSpinLock) = RET; 00461 *(PUCHAR)(KiReleaseQueuedSpinLock) = RET; 00462 00463 // 00464 // Copy the UP version of KiTryToAcquireQueuedSpinLock 00465 // over the top of the MP versin. 00466 // 00467 00468 PatchSource = &(KiTryToAcquireQueuedSpinLockUP); 00469 PatchTarget = (PUCHAR)(KiTryToAcquireQueuedSpinLock); 00470 00471 do { 00472 Byte = *PatchSource++; 00473 *PatchTarget++ = Byte; 00474 } while (Byte != RET); 00475 00476 #undef RET 00477 } 00478 KeReleaseSpinLock(&KiDispatcherLock, OldIrql); 00479 00480 #endif 00481 00482 // 00483 // Performance architecture independent initialization. 00484 // 00485 00486 KiInitSystem(); 00487 00488 // 00489 // Initialize idle thread process object and then set: 00490 // 00491 // 1. all the quantum values to the maximum possible. 00492 // 2. the process in the balance set. 00493 // 3. the active processor mask to the specified process. 00494 // 00495 00496 DirectoryTableBase[0] = 0; 00497 DirectoryTableBase[1] = 0; 00498 KeInitializeProcess(Process, 00499 (KPRIORITY)0, 00500 (KAFFINITY)(0xffffffff), 00501 &DirectoryTableBase[0], 00502 FALSE); 00503 00504 Process->ThreadQuantum = MAXCHAR; 00505 00506 } else { 00507 00508 // 00509 // Adjust global cpu setting to represent lowest of all processors 00510 // 00511 00512 FxsrPresent = ((FeatureBits & KF_FXSR) ? TRUE:FALSE); 00513 if (FxsrPresent != KeI386FxsrPresent) { 00514 // 00515 // FXSR support must be available on all processors or on none 00516 // 00517 KeBugCheckEx (MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED, KF_FXSR, 0, 0, 0); 00518 } 00519 00520 XMMIPresent = ((FeatureBits & KF_XMMI) ? TRUE:FALSE); 00521 if (XMMIPresent != KeI386XMMIPresent) { 00522 // 00523 // XMMI support must be available on all processors or on none 00524 // 00525 KeBugCheckEx (MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED, KF_XMMI, 0, 0, 0); 00526 } 00527 00528 if (NpxFlag != KeI386NpxPresent) { 00529 // 00530 // NPX support must be available on all processors or on none 00531 // 00532 00533 KeBugCheckEx (MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED, 0x387, 0, 0, 0); 00534 } 00535 00536 if ((ULONG)(Prcb->CpuType) != KeI386CpuType) { 00537 00538 if ((ULONG)(Prcb->CpuType) < KeI386CpuType) { 00539 00540 // 00541 // What is the lowest CPU type 00542 // 00543 00544 KeI386CpuType = (ULONG)Prcb->CpuType; 00545 KeProcessorLevel = (USHORT)Prcb->CpuType; 00546 } 00547 } 00548 00549 if ((KiBootFeatureBits & KF_CMPXCHG8B) && !(FeatureBits & KF_CMPXCHG8B)) { 00550 // 00551 // cmpxchg8b must be available on all processors, if installed at boot 00552 // 00553 00554 KeBugCheckEx (MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED, KF_CMPXCHG8B, 0, 0, 0); 00555 } 00556 00557 if ((KeFeatureBits & KF_GLOBAL_PAGE) && !(FeatureBits & KF_GLOBAL_PAGE)) { 00558 // 00559 // Global page support must be available on all processors, if on boot processor 00560 // 00561 00562 KeBugCheckEx (MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED, KF_GLOBAL_PAGE, 0, 0, 0); 00563 } 00564 00565 if ((KeFeatureBits & KF_PAT) && !(FeatureBits & KF_PAT)) { 00566 // 00567 // PAT must be available on all processors, if on boot processor 00568 // 00569 00570 KeBugCheckEx (MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED, KF_PAT, 0, 0, 0); 00571 } 00572 00573 if ((KeFeatureBits & KF_MTRR) && !(FeatureBits & KF_MTRR)) { 00574 // 00575 // MTRR must be available on all processors, if on boot processor 00576 // 00577 00578 KeBugCheckEx (MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED, KF_MTRR, 0, 0, 0); 00579 } 00580 00581 // 00582 // Use lowest stepping value 00583 // 00584 00585 if (Prcb->CpuStep < KeI386CpuStep) { 00586 KeI386CpuStep = Prcb->CpuStep; 00587 if (Prcb->CpuID == 0) { 00588 KeProcessorRevision = 0xFF00 | 00589 ((Prcb->CpuStep >> 8) + 'A') | 00590 (Prcb->CpuStep & 0xf); 00591 } else { 00592 KeProcessorRevision = Prcb->CpuStep; 00593 } 00594 } 00595 00596 // 00597 // Use subset of all NT feature bits available on each processor 00598 // 00599 00600 KeFeatureBits &= FeatureBits; 00601 00602 // 00603 // Lower IRQL to DISPATCH level. 00604 // 00605 00606 KeLowerIrql(DISPATCH_LEVEL); 00607 00608 } 00609 00610 // 00611 // Update processor features 00612 // 00613 00614 SharedUserData->ProcessorFeatures[PF_MMX_INSTRUCTIONS_AVAILABLE] = 00615 (KeFeatureBits & KF_MMX) ? TRUE : FALSE; 00616 00617 SharedUserData->ProcessorFeatures[PF_COMPARE_EXCHANGE_DOUBLE] = 00618 (KeFeatureBits & KF_CMPXCHG8B) ? TRUE : FALSE; 00619 00620 SharedUserData->ProcessorFeatures[PF_XMMI_INSTRUCTIONS_AVAILABLE] = 00621 ((KeFeatureBits & KF_FXSR) && (KeFeatureBits & KF_XMMI)) ? TRUE : FALSE; 00622 00623 SharedUserData->ProcessorFeatures[PF_3DNOW_INSTRUCTIONS_AVAILABLE] = 00624 (KeFeatureBits & KF_3DNOW) ? TRUE : FALSE; 00625 00626 SharedUserData->ProcessorFeatures[PF_RDTSC_INSTRUCTION_AVAILABLE] = 00627 (KeFeatureBits & KF_RDTSC) ? TRUE : FALSE; 00628 // 00629 // Initialize idle thread object and then set: 00630 // 00631 // 1. the initial kernel stack to the specified idle stack. 00632 // 2. the next processor number to the specified processor. 00633 // 3. the thread priority to the highest possible value. 00634 // 4. the state of the thread to running. 00635 // 5. the thread affinity to the specified processor. 00636 // 6. the specified processor member in the process active processors 00637 // set. 00638 // 00639 00640 KeInitializeThread(Thread, (PVOID)((ULONG)IdleStack), 00641 (PKSYSTEM_ROUTINE)NULL, (PKSTART_ROUTINE)NULL, 00642 (PVOID)NULL, (PCONTEXT)NULL, (PVOID)NULL, Process); 00643 Thread->NextProcessor = Number; 00644 Thread->Priority = HIGH_PRIORITY; 00645 Thread->State = Running; 00646 Thread->Affinity = (KAFFINITY)(1<<Number); 00647 Thread->WaitIrql = DISPATCH_LEVEL; 00648 SetMember(Number, Process->ActiveProcessors); 00649 00650 // 00651 // Initialize the processor block. (Note that some fields have been 00652 // initialized at KiInitializePcr(). 00653 // 00654 00655 Prcb->CurrentThread = Thread; 00656 Prcb->NextThread = (PKTHREAD)NULL; 00657 Prcb->IdleThread = Thread; 00658 Pcr->NtTib.StackBase = Thread->InitialStack; 00659 00660 // 00661 // call the executive initialization routine. 00662 // 00663 00664 try { 00665 ExpInitializeExecutive(Number, LoaderBlock); 00666 00667 } except (EXCEPTION_EXECUTE_HANDLER) { 00668 KeBugCheck (PHASE0_EXCEPTION); 00669 } 00670 00671 // 00672 // If the initial processor is being initialized, then compute the 00673 // timer table reciprocal value and reset the PRCB values for the 00674 // controllable DPC behavior in order to reflect any registry 00675 // overrides. 00676 // 00677 00678 if (Number == 0) { 00679 KiTimeIncrementReciprocal = KiComputeReciprocal((LONG)KeMaximumIncrement, 00680 &KiTimeIncrementShiftCount); 00681 00682 Prcb->MaximumDpcQueueDepth = KiMaximumDpcQueueDepth; 00683 Prcb->MinimumDpcRate = KiMinimumDpcRate; 00684 Prcb->AdjustDpcThreshold = KiAdjustDpcThreshold; 00685 } 00686 00687 if (Number == 0) { 00688 00689 // 00690 // Processor 0's DPC stack was temporarily allocated on 00691 // the Double Fault Stack, switch to a proper kernel 00692 // stack now. 00693 // 00694 00695 PVOID DpcStack; 00696 00697 DpcStack = MmCreateKernelStack(FALSE); 00698 00699 if (DpcStack == NULL) { 00700 KeBugCheckEx(NO_PAGES_AVAILABLE, 1, 0, 0, 0); 00701 } 00702 Prcb->DpcStack = DpcStack; 00703 00704 // 00705 // Allocate 8k IOPM bit map saved area to allow BiosCall swap 00706 // bit maps. 00707 // 00708 00709 Ki386IopmSaveArea = ExAllocatePoolWithTag(PagedPool, 00710 PAGE_SIZE * 2, 00711 ' eK'); 00712 if (Ki386IopmSaveArea == NULL) { 00713 KeBugCheckEx(NO_PAGES_AVAILABLE, 2, PAGE_SIZE * 2, 0, 0); 00714 } 00715 } 00716 00717 // 00718 // Set the priority of the specified idle thread to zero, set appropriate 00719 // member in KiIdleSummary and return to the system start up routine. 00720 // 00721 00722 KeRaiseIrql(DISPATCH_LEVEL, &OldIrql); 00723 KeSetPriorityThread(Thread, (KPRIORITY)0); 00724 00725 // 00726 // if a thread has not been selected to run on the current processors, 00727 // check to see if there are any ready threads; otherwise add this 00728 // processors to the IdleSummary 00729 // 00730 00731 KiAcquireQueuedSpinLock(KiQueuedSpinLockContext(LockQueueDispatcherLock)); 00732 if (Prcb->NextThread == (PKTHREAD)NULL) { 00733 SetMember(Number, KiIdleSummary); 00734 } 00735 KiReleaseQueuedSpinLock(KiQueuedSpinLockContext(LockQueueDispatcherLock)); 00736 00737 KeRaiseIrql(HIGH_LEVEL, &OldIrql); 00738 00739 // 00740 // This processor has initialized 00741 // 00742 00743 LoaderBlock->Prcb = (ULONG)NULL; 00744 00745 return; 00746 }

VOID KiInitializeMTRR (  IN BOOLEAN  LastProcessor  )

Definition at line 275 of file mtrr.c. References _RANGE_INFO::Capabilities, DBGMSG, _RANGE_INFO::Default, _RANGE_INFO::DefaultCachedType, ExAllocatePoolWithTag, ExFreePool(), FALSE, GROW_RANGE_TABLE, Index, KeFeatureBits, KeGetCurrentPrcb, KeGetPcr, KeInitializeSpinLock(), KF_MTRR, KiAddRange(), KiMaskToLength(), KiRangeInfo, KiRangeLock, MASK_OVERFLOW_MASK, _RANGE_INFO::MaxRange, MTRR_CAPABILITIES, MTRR_DEFAULT, MTRR_MASK_BASE, MTRR_MASK_MASK, MTRR_MSR_CAPABILITIES, MTRR_MSR_DEFAULT, MTRR_MSR_VARIABLE_BASE, MTRR_MSR_VARIABLE_MASK, MTRR_TYPE_MAX, MTRR_TYPE_UC, MTRR_TYPE_WB, MTRR_TYPE_WT, MTRR_VARIABLE_BASE, MTRR_VARIABLE_MASK, _RANGE_INFO::MtrrWorkaround, NonPagedPool, _RANGE_INFO::NoRange, NT_SUCCESS, NTSTATUS(), NULL, ONE_RANGE, _RANGE_INFO::Ranges, _RANGE_INFO::RangesValid, RDMSR(), Size, Status, TRUE, _MTRR_VARIABLE_MASK::u, _MTRR_VARIABLE_BASE::u, _MTRR_DEFAULT::u, and _MTRR_CAPABILITIES::u. : Called to incrementally initialize the physical range database feature. First processor's MTRR set is read into the physical range database. Arguments: LastProcessor - If set this is the last processor to execute this routine such that when this processor finishes, the initialization is complete. Return Value: None - if there was a problem the function KeSetPhysicalCacheTypeRange type is disabled. --*/ { BOOLEAN Status; ULONG Index, Size; MTRR_DEFAULT Default; MTRR_CAPABILITIES Capabilities; NEW_RANGE NewRange; MTRR_VARIABLE_BASE MtrrBase; MTRR_VARIABLE_MASK MtrrMask; ULONGLONG Base, Mask, Length; BOOLEAN RemoveThisType[MTRR_TYPE_MAX]; NTSTATUS NtStatus; PKPRCB Prcb; Status = TRUE; RtlZeroMemory (&NewRange, sizeof (NewRange)); NewRange.Status = STATUS_UNSUCCESSFUL; // // If this is the first processor, initialize some fields // if (KeGetPcr()->Number == 0) { KeInitializeSpinLock (&KiRangeLock); KiRangeInfo.Capabilities.u.QuadPart = RDMSR(MTRR_MSR_CAPABILITIES); KiRangeInfo.Default.u.QuadPart = RDMSR(MTRR_MSR_DEFAULT); KiRangeInfo.DefaultCachedType = MTRR_TYPE_MAX; // // If h/w mtrr support is not enabled, disable OS support // if (!KiRangeInfo.Default.u.hw.MtrrEnabled || KiRangeInfo.Capabilities.u.hw.VarCnt == 0 || KiRangeInfo.Default.u.hw.Type != MTRR_TYPE_UC) { DBGMSG("MTRR feature disabled.\n"); Status = FALSE; } else { // // If USWC type is supported by hardware, but the MTRR // feature is not set in KeFeatureBits, it is because // the HAL indicated USWC should not be used on this // machine. (Possibly due to shared memory clusters). // if (KiRangeInfo.Capabilities.u.hw.UswcSupported && ((KeFeatureBits & KF_MTRR) == 0)) { DBGMSG("KiInitializeMTRR: MTRR use globally disabled on this machine.\n"); KiRangeInfo.Capabilities.u.hw.UswcSupported = 0; } // // Allocate initial range type database // KiRangeInfo.NoRange = 0; KiRangeInfo.MaxRange = (UCHAR) KiRangeInfo.Capabilities.u.hw.VarCnt + GROW_RANGE_TABLE; KiRangeInfo.Ranges = ExAllocatePoolWithTag (NonPagedPool, sizeof(ONE_RANGE) * KiRangeInfo.MaxRange, ' eK'); RtlZeroMemory (KiRangeInfo.Ranges, sizeof(ONE_RANGE) * KiRangeInfo.MaxRange); } } // // Workaround for cpu signatures 611, 612, 616 and 617 // - if the request for setting a variable MTRR specifies // an address which is not 4M aligned or length is not // a multiple of 4M then possible problem for INVLPG inst. // Detect if workaround is required // Prcb = KeGetCurrentPrcb(); if (Prcb->CpuType == 6 && (Prcb->CpuStep == 0x0101 || Prcb->CpuStep == 0x0102 || Prcb->CpuStep == 0x0106 || Prcb->CpuStep == 0x0107 )) { if (strcmp(Prcb->VendorString, "GenuineIntel") == 0) { // // Only do this if it's an Intel part, other // manufacturers may have the same stepping // numbers but no bug. // KiRangeInfo.MtrrWorkaround = TRUE; } } // // If MTRR support disabled on first processor or if // buffer not allocated then fall through // if (!KiRangeInfo.Ranges){ Status = FALSE; } else { // // Verify MTRR support is symmetric // Capabilities.u.QuadPart = RDMSR(MTRR_MSR_CAPABILITIES); if ((Capabilities.u.hw.UswcSupported) && ((KeFeatureBits & KF_MTRR) == 0)) { DBGMSG ("KiInitializeMTRR: setting UswcSupported FALSE\n"); Capabilities.u.hw.UswcSupported = 0; } Default.u.QuadPart = RDMSR(MTRR_MSR_DEFAULT); if (Default.u.QuadPart != KiRangeInfo.Default.u.QuadPart || Capabilities.u.QuadPart != KiRangeInfo.Capabilities.u.QuadPart) { DBGMSG ("KiInitializeMTRR: asymmetric mtrr support\n"); Status = FALSE; } } NewRange.Status = STATUS_SUCCESS; // // MTRR registers should be identically set on each processor. // Ranges should be added to the range database only for one // processor. // if (Status && (KeGetPcr()->Number == 0)) { #if IDBG KiDumpMTRR ("Processor MTRR:", NULL); #endif // // Read current MTRR settings for various cached range types // and add them to the range database // for (Index=0; Index < Capabilities.u.hw.VarCnt; Index++) { MtrrBase.u.QuadPart = RDMSR(MTRR_MSR_VARIABLE_BASE+Index*2); MtrrMask.u.QuadPart = RDMSR(MTRR_MSR_VARIABLE_MASK+Index*2); Mask = MtrrMask.u.QuadPart & MTRR_MASK_MASK; Base = MtrrBase.u.QuadPart & MTRR_MASK_BASE; // // Note - the variable MTRR Mask does NOT contain the length // spanned by the variable MTRR. Thus just checking the Valid // Bit should be sufficient for identifying a valid MTRR. // if (MtrrMask.u.hw.Valid) { Length = KiMaskToLength(Mask); // // Check for non-contiguous MTRR mask. // if ((Mask + Length) & MASK_OVERFLOW_MASK) { DBGMSG ("KiInitializeMTRR: Found non-contiguous MTRR mask!\n"); Status = FALSE; } // // Add this MTRR to the range database // Base &= Mask; KiAddRange ( &NewRange, Base, Base + Length - 1, (UCHAR) MtrrBase.u.hw.Type ); // // Check for default cache type // if (MtrrBase.u.hw.Type == MTRR_TYPE_WB) { KiRangeInfo.DefaultCachedType = MTRR_TYPE_WB; } if (KiRangeInfo.DefaultCachedType == MTRR_TYPE_MAX && MtrrBase.u.hw.Type == MTRR_TYPE_WT) { KiRangeInfo.DefaultCachedType = MTRR_TYPE_WT; } } } // // If a default type for "cached" was not found, assume write-back // if (KiRangeInfo.DefaultCachedType == MTRR_TYPE_MAX) { DBGMSG ("KiInitializeMTRR: assume write-back\n"); KiRangeInfo.DefaultCachedType = MTRR_TYPE_WB; } } // // Done // if (!NT_SUCCESS(NewRange.Status)) { Status = FALSE; } if (!Status) { DBGMSG ("KiInitializeMTRR: OS support for MTRRs disabled\n"); if (KiRangeInfo.Ranges != NULL) { ExFreePool (KiRangeInfo.Ranges); KiRangeInfo.Ranges = NULL; } } else { // if last processor indicate initialization complete if (LastProcessor) { KiRangeInfo.RangesValid = TRUE; } } }

VOID KiInitializePAT (  VOID   )

Definition at line 119 of file pat.c. References ASSERT, _NEW_PAT::Attributes, HIGH_LEVEL, _PAT::hw, KeActiveProcessors, KeFeatureBits, KeGetCurrentPrcb, KeRaiseIrql(), KF_PAT, KiIpiStallOnPacketTargets(), KiLoadPAT(), KiLoadPATTarget(), KiLockContextSwap, KiUnlockContextSwap, MmEnablePAT(), NULL, PAT_TYPE_STRONG_UC, PAT_TYPE_USWC, PAT_TYPE_WB, PAT_TYPE_WEAK_UC, _NEW_PAT::Processor, Size, _NEW_PAT::TargetCount, and _NEW_PAT::TargetPhase. : Initialize the Page Attribute Table (PAT) on all processors. PAT is setup to provide WB, WC, STRONG_UC and WEAK_UC as the memory types such that mm macros for enabling/disabling/querying caching (MI_DISABLE_CACHING, MI_ENABLE_CACHING and MI_IS_CACHING_ENABLED) are unaffected. PAT_Entry PAT Index PCD PWT Memory Type 0 0 0 0 WB 1 0 0 1 WC * 2 0 1 0 WEAK_UC 3 0 1 1 STRONG_UC 4 1 0 0 WB 5 1 0 1 WC * 6 1 1 0 WEAK_UC 7 1 1 1 STRONG_UC N.B. The caller must have the PAGELK code locked and ensure that the PAT feature is supported. Arguments: None. Return Value: None. --*/ { PAT PatAttributes; ULONG Size; KIRQL OldIrql, NewIrql; PKPRCB Prcb; NEW_PAT NewPAT; KAFFINITY TargetProcessors; ASSERT ((KeFeatureBits & KF_PAT) != 0); // // Initialize the PAT // PatAttributes.hw.Pat[0] = PAT_TYPE_WB; PatAttributes.hw.Pat[1] = PAT_TYPE_USWC; PatAttributes.hw.Pat[2] = PAT_TYPE_WEAK_UC; PatAttributes.hw.Pat[3] = PAT_TYPE_STRONG_UC; PatAttributes.hw.Pat[4] = PAT_TYPE_WB; PatAttributes.hw.Pat[5] = PAT_TYPE_USWC; PatAttributes.hw.Pat[6] = PAT_TYPE_WEAK_UC; PatAttributes.hw.Pat[7] = PAT_TYPE_STRONG_UC; // // Synchronize with other IPI functions which may stall // KiLockContextSwap(&OldIrql); Prcb = KeGetCurrentPrcb(); NewPAT.Attributes = PatAttributes; NewPAT.TargetCount = 0; NewPAT.TargetPhase = &Prcb->ReverseStall; NewPAT.Processor = Prcb->Number; #if !defined(NT_UP) // // Collect all the (other) processors // TargetProcessors = KeActiveProcessors & ~Prcb->SetMember; if (TargetProcessors != 0) { KiIpiSendSynchronousPacket ( Prcb, TargetProcessors, KiLoadPATTarget, (PVOID) (&NewPAT), NULL, NULL ); // // Wait for all processors to be collected // KiIpiStallOnPacketTargets(TargetProcessors); // // All processors are now waiting. Raise to high level to // ensure this processor doesn't enter the debugger due to // some interrupt service routine. // KeRaiseIrql (HIGH_LEVEL, &NewIrql); // // There's no reason for any debug events now, so signal // the other processors that they can all begin the PAT update // Prcb->ReverseStall += 1; } #endif // // Update PAT // KiLoadPAT(&NewPAT); // // Release ContextSwap lock and lower to initial irql // KiUnlockContextSwap(OldIrql); MmEnablePAT(); return; }

VOID KiInitializePcr (  IN ULONG  Processor, IN PKPCR  Pcr, IN PKIDTENTRY  Idt, IN PKGDTENTRY  Gdt, IN PKTSS  Tss, IN PKTHREAD  Thread, IN PVOID  DpcStack )

Definition at line 749 of file kernlini.c. References KiProcessorBlock, PCR_MAJOR_VERSION, PCR_MINOR_VERSION, PRCB_MAJOR_VERSION, PRCB_MINOR_VERSION, and TRUE. Referenced by KeStartAllProcessors(). 00761 : 00762 00763 This function is called to initialize the PCR for a processor. It 00764 simply stuffs values into the PCR. (The PCR is not inited statically 00765 because the number varies with the number of processors.) 00766 00767 Note that each processor has its own IDT, GDT, and TSS as well as PCR! 00768 00769 Arguments: 00770 00771 Processor - Processor whose PCR to initialize. 00772 00773 Pcr - Linear address of PCR. 00774 00775 Idt - Linear address of i386 IDT. 00776 00777 Gdt - Linear address of i386 GDT. 00778 00779 Tss - Linear address (NOT SELECTOR!) of the i386 TSS. 00780 00781 Thread - Dummy thread object to use very early on. 00782 00783 Return Value: 00784 00785 None. 00786 00787 --*/ 00788 { 00789 // set version values 00790 00791 Pcr->MajorVersion = PCR_MAJOR_VERSION; 00792 Pcr->MinorVersion = PCR_MINOR_VERSION; 00793 00794 Pcr->PrcbData.MajorVersion = PRCB_MAJOR_VERSION; 00795 Pcr->PrcbData.MinorVersion = PRCB_MINOR_VERSION; 00796 00797 Pcr->PrcbData.BuildType = 0; 00798 00799 #if DBG 00800 Pcr->PrcbData.BuildType |= PRCB_BUILD_DEBUG; 00801 #endif 00802 00803 #ifdef NT_UP 00804 Pcr->PrcbData.BuildType |= PRCB_BUILD_UNIPROCESSOR; 00805 #endif 00806 00807 #if defined (_X86PAE_) 00808 if (Processor == 0) { 00809 // 00810 // PAE feature must be initialized prior to the first HAL call. 00811 // 00812 00813 SharedUserData->ProcessorFeatures[PF_PAE_ENABLED] = TRUE; 00814 } 00815 #endif 00816 00817 // Basic addressing fields 00818 00819 Pcr->SelfPcr = Pcr; 00820 Pcr->Prcb = &(Pcr->PrcbData); 00821 00822 // Thread control fields 00823 00824 Pcr->NtTib.ExceptionList = EXCEPTION_CHAIN_END; 00825 Pcr->NtTib.StackBase = 0; 00826 Pcr->NtTib.StackLimit = 0; 00827 Pcr->NtTib.Self = 0; 00828 00829 Pcr->PrcbData.CurrentThread = Thread; 00830 00831 // 00832 // Init Prcb.Number and ProcessorBlock such that Ipi will work 00833 // as early as possible. 00834 // 00835 00836 Pcr->PrcbData.Number = (UCHAR)Processor; 00837 Pcr->PrcbData.SetMember = 1 << Processor; 00838 KiProcessorBlock[Processor] = Pcr->Prcb; 00839 00840 Pcr->Irql = 0; 00841 00842 // Machine structure addresses 00843 00844 Pcr->GDT = Gdt; 00845 Pcr->IDT = Idt; 00846 Pcr->TSS = Tss; 00847 Pcr->PrcbData.DpcStack = DpcStack; 00848 00849 return; 00850 }

VOID KiInitializeTSS (  IN PKTSS  Tss  )

Definition at line 944 of file kernlini.c. 00950 : 00951 00952 This function is called to initialize the TSS for a processor. 00953 It will set the static fields of the TSS. (ie Those fields that 00954 the part reads, and for which NT uses constant values.) 00955 00956 The dynamic fields (Esp0 and CR3) are set in the context swap 00957 code. 00958 00959 Arguments: 00960 00961 Tss - Linear address of the Task State Segment. 00962 00963 Return Value: 00964 00965 None. 00966 00967 --*/ 00968 { 00969 00970 // Set IO Map base address to indicate no IO map present. 00971 00972 // N.B. -1 does not seem to be a valid value for the map base. If this 00973 // value is used, byte immediate in's and out's will actually go 00974 // the hardware when executed in V86 mode. 00975 00976 Tss->IoMapBase = KiComputeIopmOffset(IO_ACCESS_MAP_NONE); 00977 00978 // Set flags to 0, which in particular disables traps on task switches. 00979 00980 Tss->Flags = 0; 00981 00982 00983 // Set LDT and Ss0 to constants used by NT. 00984 00985 Tss->LDT = 0; 00986 Tss->Ss0 = KGDT_R0_DATA; 00987 00988 return; 00989 }

VOID KiInitializeTSS2 (  IN PKTSS  Tss, IN PKGDTENTRY  TssDescriptor )

Definition at line 992 of file kernlini.c. References NULL. 00999 : 01000 01001 Do part of TSS init we do only once. 01002 01003 Arguments: 01004 01005 Tss - Linear address of the Task State Segment. 01006 01007 TssDescriptor - Linear address of the descriptor for the TSS. 01008 01009 Return Value: 01010 01011 None. 01012 01013 --*/ 01014 { 01015 PUCHAR p; 01016 ULONG i; 01017 ULONG j; 01018 01019 // 01020 // Set limit for TSS 01021 // 01022 01023 if (TssDescriptor != NULL) { 01024 TssDescriptor->LimitLow = sizeof(KTSS) - 1; 01025 TssDescriptor->HighWord.Bits.LimitHi = 0; 01026 } 01027 01028 // 01029 // Initialize IOPMs 01030 // 01031 01032 for (i = 0; i < IOPM_COUNT; i++) { 01033 p = (PUCHAR)(Tss->IoMaps[i].IoMap); 01034 01035 for (j = 0; j < PIOPM_SIZE; j++) { 01036 p[j] = (UCHAR)-1; 01037 } 01038 } 01039 01040 // 01041 // Initialize Software Interrupt Direction Maps 01042 // 01043 01044 for (i = 0; i < IOPM_COUNT; i++) { 01045 p = (PUCHAR)(Tss->IoMaps[i].DirectionMap); 01046 for (j = 0; j < INT_DIRECTION_MAP_SIZE; j++) { 01047 p[j] = 0; 01048 } 01049 // dpmi requires special case for int 2, 1b, 1c, 23, 24 01050 p[0] = 4; 01051 p[3] = 0x18; 01052 p[4] = 0x18; 01053 } 01054 01055 // 01056 // Initialize the map for IO_ACCESS_MAP_NONE 01057 // 01058 p = (PUCHAR)(Tss->IntDirectionMap); 01059 for (j = 0; j < INT_DIRECTION_MAP_SIZE; j++) { 01060 p[j] = 0; 01061 } 01062 01063 // dpmi requires special case for int 2, 1b, 1c, 23, 24 01064 p[0] = 4; 01065 p[3] = 0x18; 01066 p[4] = 0x18; 01067 01068 return; 01069 }

BOOLEAN KiInitMachineDependent (  VOID   )

Definition at line 1691 of file kernlini.c. References ASSERT, CPUID(), FALSE, HalFrameBufferCachingInformation, HalQuerySystemInformation, IDENTITY_MAP, Index, KeActiveProcessors, KeDelayExecutionThread(), KeFeatureBits, KeGetCurrentPrcb, KeNumberProcessors, KeQueryPerformanceCounter(), KeRevertToUserAffinityThread(), KernelMode, KeSetSystemAffinityThread(), KeZeroPage, KeZeroPageFromIdleThread, KF_AMDK6MTRR, KF_FXSR, KF_GLOBAL_PAGE, KF_LARGE_PAGE, KF_MTRR, KF_PAT, KF_RDTSC, KF_WORKING_PTE, KF_XMMI, Ki386ClearIdentityMap(), Ki386CreateIdentityMap(), Ki386EnableCurrentLargePage(), Ki386EnableCurrentLargePageEnd, Ki386EnableFxsr(), Ki386EnableGlobalPage(), Ki386EnableTargetLargePage(), Ki386EnableXMMIExceptions(), Ki386UseSynchronousTbFlush(), KiAmdK6InitializeMTRR(), KiI386PentiumLockErrataFixup(), KiI386PentiumLockErrataPresent, KiInitializeMTRR(), KiInitializePAT(), KiIpiGenericCall(), KiXMMIZeroPage(), KiXMMIZeroPageNoSave(), L, MAX_ATTEMPTS, NT_SUCCESS, NTSTATUS(), NULL, PKIPI_BROADCAST_WORKER, RDTSC(), ScPatchFxb, ScPatchFxe, Size, Status, TRUE, and USHORT. { KAFFINITY ActiveProcessors, CurrentAffinity; ULONG NumberProcessors; IDENTITY_MAP IdentityMap; ULONG Index; ULONG Average; ULONG Junk; struct { LARGE_INTEGER PerfStart; LARGE_INTEGER PerfEnd; LONGLONG PerfDelta; LARGE_INTEGER PerfFreq; LONGLONG TSCStart; LONGLONG TSCEnd; LONGLONG TSCDelta; ULONG MHz; } Samples[MAX_ATTEMPTS], *pSamp; PUCHAR PatchLocation; // // If PDE large page is supported, enable it. // // We enable large pages before global pages to make TLB invalidation // easier while turning on large pages. // if (KeFeatureBits & KF_LARGE_PAGE) { if (Ki386CreateIdentityMap(&IdentityMap, &Ki386EnableCurrentLargePage, &Ki386EnableCurrentLargePageEnd )) { KiIpiGenericCall ( (PKIPI_BROADCAST_WORKER) Ki386EnableTargetLargePage, (ULONG)(&IdentityMap) ); } // // Always call Ki386ClearIdentityMap() to free any memory allocated // Ki386ClearIdentityMap(&IdentityMap); } // // If PDE/PTE global page is supported, enable it // if (KeFeatureBits & KF_GLOBAL_PAGE) { NumberProcessors = KeNumberProcessors; KiIpiGenericCall ( (PKIPI_BROADCAST_WORKER) Ki386EnableGlobalPage, (ULONG)(&NumberProcessors) ); } #if !defined(NT_UP) // // If some processor doesn't have proper MP PTE implementation, // then use a synchronous TB shoot down handler // if (!(KeFeatureBits & KF_WORKING_PTE)) { NumberProcessors = KeNumberProcessors; KiIpiGenericCall ( (PKIPI_BROADCAST_WORKER) Ki386UseSynchronousTbFlush, (ULONG)(&NumberProcessors) ); } #endif // // If PAT or MTRR supported but the HAL indicates it shouldn't // be used (eg on a Shared Memory Cluster), drop the feature. // if (KeFeatureBits & (KF_PAT | KF_MTRR)) { NTSTATUS Status; BOOLEAN UseFrameBufferCaching; ULONG Size; Status = HalQuerySystemInformation( HalFrameBufferCachingInformation, sizeof(UseFrameBufferCaching), &UseFrameBufferCaching, &Size ); if (NT_SUCCESS(Status) && (UseFrameBufferCaching == FALSE)) { // // Hal says don't use. // KeFeatureBits &= ~(KF_PAT | KF_MTRR); } } // // If PAT is supported then initialize it. // if (KeFeatureBits & KF_PAT) { KiInitializePAT(); } // // Compute each processors approximate mhz // // // If FXSR feature is supported, set OSFXSR (bit 9) in CR4 // if (KeFeatureBits & KF_FXSR) { NumberProcessors = KeNumberProcessors; KiIpiGenericCall ( (PKIPI_BROADCAST_WORKER) Ki386EnableFxsr, (ULONG)(&NumberProcessors) ); // // If XMMI feature is supported, // a. Hook int 19 handler // b. Set OSXMMEXCPT (bit 10) in CR4 // c. Enable use of fast XMMI based zero page routines. // if (KeFeatureBits & KF_XMMI) { KiIpiGenericCall ( (PKIPI_BROADCAST_WORKER) Ki386EnableXMMIExceptions, (ULONG)(&NumberProcessors) ); KeZeroPage = KiXMMIZeroPage; KeZeroPageFromIdleThread = KiXMMIZeroPageNoSave; } } else { #ifndef NT_UP // // Patch the fxsave instruction in SwapContext to use // "fnsave {dd, 31}, fwait {9b}" // ASSERT( ((ULONG)&ScPatchFxe-(ULONG)&ScPatchFxb) >= 3); PatchLocation = (PUCHAR)&ScPatchFxb; *PatchLocation++ = 0xdd; *PatchLocation++ = 0x31; *PatchLocation++ = 0x9b; while (PatchLocation < (PUCHAR)&ScPatchFxe) { // // Put nop's in the remaining bytes // *PatchLocation++ = 0x90; } #endif } ActiveProcessors = KeActiveProcessors; for (CurrentAffinity=1; ActiveProcessors; CurrentAffinity <<= 1) { if (ActiveProcessors & CurrentAffinity) { // // Switch to that processor, and remove it from the // remaining set of processors // ActiveProcessors &= ~CurrentAffinity; KeSetSystemAffinityThread(CurrentAffinity); // // Determine the MHz for the processor // KeGetCurrentPrcb()->MHz = 0; if (KeFeatureBits & KF_RDTSC) { Index = 0; pSamp = Samples; for (; ;) { // // Collect a new sample // Delay the thread a "long" amount and time it with // a time source and RDTSC. // CPUID (0, &Junk, &Junk, &Junk, &Junk); pSamp->PerfStart = KeQueryPerformanceCounter (NULL); pSamp->TSCStart = RDTSC(); pSamp->PerfFreq.QuadPart = -50000; KeDelayExecutionThread (KernelMode, FALSE, &pSamp->PerfFreq); CPUID (0, &Junk, &Junk, &Junk, &Junk); pSamp->PerfEnd = KeQueryPerformanceCounter (&pSamp->PerfFreq); pSamp->TSCEnd = RDTSC(); // // Calculate processors MHz // pSamp->PerfDelta = pSamp->PerfEnd.QuadPart - pSamp->PerfStart.QuadPart; pSamp->TSCDelta = pSamp->TSCEnd - pSamp->TSCStart; pSamp->MHz = (ULONG) ((pSamp->TSCDelta * pSamp->PerfFreq.QuadPart + 500000L) / (pSamp->PerfDelta * 1000000L)); // // If last 2 samples matched within a MHz, done // if (Index) { if (pSamp->MHz == pSamp[-1].MHz || pSamp->MHz == pSamp[-1].MHz + 1 || pSamp->MHz == pSamp[-1].MHz - 1) { break; } } // // Advance to next sample // pSamp += 1; Index += 1; // // If too many samples, then something is wrong // if (Index >= MAX_ATTEMPTS) { #if DBG // // Temp breakpoint to see where this is failing // and why // DbgBreakPoint(); #endif Average = 0; for (Index = 0; Index < MAX_ATTEMPTS; Index++) { Average += Samples[Index].MHz; } pSamp[-1].MHz = Average / MAX_ATTEMPTS; break; } } KeGetCurrentPrcb()->MHz = (USHORT) pSamp[-1].MHz; } // // If MTRRs are supported and PAT not supported, initialize MTRRs // per processor // if (!(KeFeatureBits & KF_PAT) && (KeFeatureBits & KF_MTRR)) { KiInitializeMTRR ( (BOOLEAN) (ActiveProcessors ? FALSE : TRUE)); } // // If the processor is a AMD K6 with MTRR support then // perform processor specific initialization. // if (KeFeatureBits & KF_AMDK6MTRR) { KiAmdK6InitializeMTRR(); } // // Apply Pentium workaround if needed // if (KiI386PentiumLockErrataPresent) { KiI386PentiumLockErrataFixup (); } } } KeRevertToUserAffinityThread(); return TRUE; }

BOOLEAN KiIsNpxPresent (  VOID   )

Referenced by KiInitializeKernel().

NTSTATUS KiMoveRegTree (  HANDLE  Source, HANDLE  Dest )

Definition at line 2297 of file kernlini.c. References KeyName, NT_SUCCESS, NtDeleteKey(), NTSTATUS(), NULL, ObjectAttributes, Status, USHORT, and ValueName. Referenced by KeSetup80387OrEmulate(). { NTSTATUS Status; PKEY_BASIC_INFORMATION KeyInformation; PKEY_VALUE_FULL_INFORMATION KeyValue; OBJECT_ATTRIBUTES ObjectAttributes; HANDLE SourceChild; HANDLE DestChild; ULONG ResultLength; UCHAR buffer[1024]; // hmm.... UNICODE_STRING ValueName; UNICODE_STRING KeyName; KeyValue = (PKEY_VALUE_FULL_INFORMATION)buffer; // // Move values from source node to dest node // for (; ;) { // // Get first value // Status = ZwEnumerateValueKey(Source, 0, KeyValueFullInformation, buffer, sizeof (buffer), &ResultLength); if (!NT_SUCCESS(Status)) { break; } // // Write value to dest node // ValueName.Buffer = KeyValue->Name; ValueName.Length = (USHORT) KeyValue->NameLength; ZwSetValueKey( Dest, &ValueName, KeyValue->TitleIndex, KeyValue->Type, buffer+KeyValue->DataOffset, KeyValue->DataLength ); // // Delete value and get first value again // Status = ZwDeleteValueKey (Source, &ValueName); if (!NT_SUCCESS(Status)) { break; } } // // Enumerate node's children and apply ourselves to each one // KeyInformation = (PKEY_BASIC_INFORMATION)buffer; for (; ;) { // // Open node's first key // Status = ZwEnumerateKey( Source, 0, KeyBasicInformation, KeyInformation, sizeof (buffer), &ResultLength ); if (!NT_SUCCESS(Status)) { break; } KeyName.Buffer = KeyInformation->Name; KeyName.Length = (USHORT) KeyInformation->NameLength; InitializeObjectAttributes( &ObjectAttributes, &KeyName, OBJ_CASE_INSENSITIVE, Source, NULL ); Status = ZwOpenKey( &SourceChild, KEY_ALL_ACCESS, &ObjectAttributes ); if (!NT_SUCCESS(Status)) { break; } // // Create key in dest tree // InitializeObjectAttributes( &ObjectAttributes, &KeyName, OBJ_CASE_INSENSITIVE, Dest, NULL ); Status = ZwCreateKey( &DestChild, KEY_ALL_ACCESS, &ObjectAttributes, 0, NULL, REG_OPTION_VOLATILE, NULL ); if (!NT_SUCCESS(Status)) { break; } // // Move subtree // Status = KiMoveRegTree(SourceChild, DestChild); ZwClose(DestChild); ZwClose(SourceChild); if (!NT_SUCCESS(Status)) { break; } // // Loop and get first key. (old first key was delete by the // call to KiMoveRegTree). // } // // Remove source node // return NtDeleteKey (Source); }

VOID KiSetCR0Bits (  VOID   )

Referenced by KiInitializeKernel().

VOID KiSetProcessorType (  VOID   )

Referenced by KiInitializeKernel().

VOID KiSwapIDT (   )

Definition at line 1072 of file kernlini.c. References IDT, Index, and USHORT. 01077 : 01078 01079 This function is called to edit the IDT. It swaps words of the address 01080 and access fields around into the format the part actually needs. 01081 This allows for easy static init of the IDT. 01082 01083 Note that this procedure edits the current IDT. 01084 01085 Arguments: 01086 01087 None. 01088 01089 Return Value: 01090 01091 None. 01092 01093 --*/ 01094 { 01095 LONG Index; 01096 USHORT Temp; 01097 01098 // 01099 // Rearrange the entries of IDT to match i386 interrupt gate structure 01100 // 01101 01102 for (Index = 0; Index <= MAXIMUM_IDTVECTOR; Index += 1) { 01103 Temp = IDT[Index].Selector; 01104 IDT[Index].Selector = IDT[Index].ExtendedOffset; 01105 IDT[Index].ExtendedOffset = Temp; 01106 } 01107 }

VOID KiSwapIDT (  VOID   )

VOID FASTCALL KiXMMIZeroPage (  PVOID  PageBase  )

Referenced by KiInitMachineDependent().

VOID FASTCALL KiXMMIZeroPageNoSave (  PVOID  PageBase  )

Referenced by KiInitMachineDependent().

VOID FASTCALL KiZeroPage (  PVOID  PageBase  )

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Variable Documentation

KSPIN_LOCK CcMasterSpinLock

Definition at line 47 of file kernlini.c.

KSPIN_LOCK CcVacbSpinLock

Definition at line 48 of file kernlini.c.

WCHAR CmDisabledFloatingPointProcessor[]

Definition at line 184 of file kernlini.c.

UCHAR CmpAmdID[]

Definition at line 187 of file kernlini.c.

UCHAR CmpCyrixID[]

Definition at line 185 of file kernlini.c.

UCHAR CmpIntelID[]

Definition at line 186 of file kernlini.c.

KIDTENTRY IDT[]

Definition at line 243 of file kernlini.c. Referenced by KiSwapIDT().

ULONG KeI386ForceNpxEmulation

Definition at line 183 of file kernlini.c. Referenced by KeSetup80387OrEmulate().

BOOLEAN KeI386XMMIPresent

Definition at line 208 of file kernlini.c.

KE_ZERO_PAGE_ROUTINE KeZeroPage = KiZeroPage

Definition at line 228 of file kernlini.c. Referenced by KiInitMachineDependent(), and MiZeroPhysicalPage().

KE_ZERO_PAGE_ROUTINE KeZeroPageFromIdleThread = KiZeroPage

Definition at line 229 of file kernlini.c. Referenced by KiInitMachineDependent(), and MmZeroPageThread().

PVOID Ki386IopmSaveArea

Definition at line 182 of file kernlini.c. Referenced by Ke386CallBios(), and KiInitializeKernel().

PVOID Ki387RoundModeTable

Definition at line 181 of file kernlini.c. Referenced by KeSetup80387OrEmulate().

ULONG Ki486CompatibilityLock

Definition at line 237 of file kernlini.c. Referenced by KiInitializeKernel().

BOOLEAN KiI386PentiumLockErrataPresent = FALSE

Definition at line 173 of file kernlini.c. Referenced by KiInitMachineDependent().

BOOLEAN KiIgnoreUnexpectedTrap07 = FALSE

Definition at line 174 of file kernlini.c.

KSPIN_LOCK MmPfnLock

Definition at line 49 of file kernlini.c.

KSPIN_LOCK MmSystemSpaceLock

Definition at line 50 of file kernlini.c.

PVOID ScPatchFxb

Definition at line 190 of file kernlini.c. Referenced by KiInitMachineDependent().

PVOID ScPatchFxe

Definition at line 191 of file kernlini.c. Referenced by KiInitMachineDependent().

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